Hi Sir,
There is a parallel video bus which connects to VIN[x] of DM8168 in our design. The video bus operates at 1080P. The clock rat is 148.5MHz.The video data are translated at clock falling edge. We think this implementation can get the max tolerance for both setup time and hold time.
We measured the setup time and hold time by this implementation. The setup time is around 3ns~2.6ns. But the spec of HDVPSS of DM8168 is 3.75ns. This spec is a little strange to me. As my previous experience, the setup time of other devices almost is around 1ns~2ns. It is less the half of clock cycle. But the spec of DM8168 is larger than half of clock cycle.
We have done a lot of test based on the current design. We didn’t find any problem. So, I am not sure if I need to change the design to meet the sepc of HDVPSS of DM8168 (3.75ns of setup time). Could you comment if 3ns~2.6ns of setup time is enough for HDVPSS?
