This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320DM8168 : skew the leveling can tolerate between CLK and DQS

Hello,

Can I know how much skew the leveling can tolerate between CLK and DQS for the TMS320DM8168. The routing guidelines do not specify this information.

Thanks

Kishen Someshwar

  • Hi Kishen,

    No such info in datasheet, because CLK and DQSx are in different timing net classes. So there is no requirement for min/max skew between CLK and DQSx.

    Regards,
    Pavel
  • FAE response:

    Perhaps the Application Engineer is not familiar with the JEDEC standard.  There is in fact 3 very clear specs tDQSS, tDSS, and tDSH that define the edge of DQS to CLK.  Your routing rules do not address this.   And that is what I am trying to find out, given the differences in length between my DQS and CLK. On one lane, my clock is  1.36 in or about 250 ps longer than DQS. 

    So it is not clear what your limits are to your software leveling which is supposed to manage these differences. I need to know these limits.

  • Kishon,

    Please research the concept of leveling as it applies to DDR3 implementations.  Yes, there are timing terms tDQSS, tDSS, and tDSH that define the edge of DQS relative to CLK.  However, these specs must be met after write leveling is completed.  DDR3 topologies use a concept called fly-by routing.  Fly-by routing coupled with write leveling enables the data rates supported by DDR3.  By definition, the routed lengths of the CLK group at each SDRAM and the individual DATA group (including DQS) at each SDRAM will have large differences that can be in the inches.  Leveling can resolve this.  Please refer to the routing skew limits (as well as other routing rules) in the Data Manual.  These must be met.  They are sufficient for robust DDR3 operation.  Please refer to the following wiki link for more tools to help with this process:

    processors.wiki.ti.com/.../DM816x_C6A816x_AM389x_DDR3_Init

    Tom