DM8168 McBSP not able to configure the registers?

Hi Chou,

From which phase you are trying to write the McBSP registers? u-boot, linux kernel, user space?

Regards,
Pavel

See also if the below e2e threads will be in help:

e2e.ti.com/.../243306
e2e.ti.com/.../468960

Regards,
Pavel

Hi Pavel,

   I am trying to write the MCBSP registers in linux kernel. When I set SYSCON(0x470000010) to 0x214, then the value is 0x210.

Hi Pavel,
it is right value with offset 0x8C(full address 0x4700008C) for the McBSP SYSCONFIG register.
do the all register error offset in TRM? if true ,how to fix this ?

I do not see/find other wrong offsets.

Regards,
Pavel

Hi Pavel,I set the mcbsp register like this:
mcbsp_config.rcr1 = RCR1_RFRLEN1(TI81XX_MCBSP_WORD_8) |
RCR1_RWDLEN1(TI81XX_MCBSP_WORD_8);
mcbsp_config.xcr1 = XCR1_XFRLEN1(TI81XX_MCBSP_WORD_8) |
XCR1_XWDLEN1(TI81XX_MCBSP_WORD_8);
mcbsp_config.rcr2 = RCR2_RDATDLY(1);
mcbsp_config.xcr2 = XCR2_XDATDLY(1); mcbsp_config.pcr0 = PCR_CLKRP;
mcbsp_config.srgr1 = SRGR1_FWID(1) |
SRGR1_CLKGDV(1) ;
mcbsp_config.srgr2 = SRGR2_FPER(16);
// RINT generated when the RRDY bit (SPCR1_REG[1]) changes from 0 to 1
mcbsp_config.spcr1 = SPCR1_RINTM(0);// |
mcbsp_config.spcr2 = SPCR2_FREE;
mcbsp_config.rccr = 0; //RCCR_RDMAEN disable
EMDA seting like this: where B_CNT = 1 ;channel=15
param.opt = TCINTEN | // Transfer complete interrupt is enabled
EDMA_TCC(channel) | // Transfer complete code
(0 << 8) | // FWID FIFO width is 8-bit
1; // Source address mode. Constant addressing (CONST) mode
param.src = 0x47000000;//TI816x_MCBSP_BASE + MCBSP_DRR ;
param.a_b_cnt = (B_CNT << 16) | 0x1; param.dst = buf_phyaddr;
param.src_dst_bidx = 0x00010000; // src_inx = 0 fix src register
param.link_bcntrld = (B_CNT << 16) | 0xFFFF ;
param.src_dst_cidx = 0 ; param.ccnt = 1;
when i call edma_start() function ,the rx _edma_callback function is trigger .
as the mcbsp register seting ,RCCR_RDMAEN had been disabled .
is there any error value for mcbsp register?

Hi Chou,

I am not sure I understand you question here. Do you mean you can not make successful EDMA transfer with McBSP? Can you provide more details?

Do you work with EZSDK or DVR RDK or CCS based project or else?

Regards,
Pavel

Hi Pavel.

yes ,i can not make sucessful EDMA transfer with McBSP in DVR RDK 4.0.

mcbsp_config.rccr = 0; means disable transmit DMA request. but when i call edma_start() function,the EDMA still work.

here is the configure for McBSP register :

mcbsp_config.rcr1 = RCR1_RFRLEN1(TI81XX_MCBSP_WORD_8) |
                                   RCR1_RWDLEN1(TI81XX_MCBSP_WORD_8);
mcbsp_config.xcr1 = XCR1_XFRLEN1(TI81XX_MCBSP_WORD_8) |
                                   XCR1_XWDLEN1(TI81XX_MCBSP_WORD_8);
mcbsp_config.rcr2 = RCR2_RDATDLY(1);
mcbsp_config.xcr2 = XCR2_XDATDLY(1);

mcbsp_config.pcr0 = PCR_CLKRP;
mcbsp_config.srgr1 = SRGR1_FWID(1) |
                                      SRGR1_CLKGDV(1) ;
mcbsp_config.srgr2 = SRGR2_FPER(16);
// RINT generated when the RRDY bit (SPCR1_REG[1]) changes from 0 to 1
mcbsp_config.spcr1 = SPCR1_RINTM(0);// |
mcbsp_config.spcr2 = SPCR2_FREE;
mcbsp_config.rccr = 0; //RCCR_RDMAEN disable

 

Chou,

chou tom said:

i can not make sucessful EDMA transfer

Please provide me McBSP register dump at the below format:

SYSCONFIG_REG = 0x.......
IRQSTATUS_REG = 0x....
IRQENABLE_REG = 0x....
DRR_REG = 0x....
SPCR2_REG = 0x....
SPCR1_REG = 0x....
PCR_REG = 0x...
RCCR_REG = 0x...
RBUFFSTAT_REG = 0x..
DMARXENABLE_SET = 0x....
DMARXENABLE_CLR = 0x...

Please provide me and the full physical address that you are using for each of these registers.

chou tom said:

mcbsp_config.rccr = 0; means disable transmit DMA request. but when i call edma_start() function,the EDMA still work

You state that you can not make successful EDMA transfer, and at the same time you state that EDMA work! Can you elaborate on that point? Do you enter into sleep mode and than wait for the McBSP to generate DMA wake up request?

Regards,
Pavel

McBSP register dump at the below format:
Name(full physical address ) = value. e.g.SYSCON(0x4700008C)= 0x00000214
SYSCON(0x4700008C)=0x00000214

DRR(0x47000000)=0x00000000
DXR(0x47000008)=0x00000000

SPCR2(0x47000010)=0x00000083
SPCR1(0x47000014)=0x00000007

RCR2(0x47000018)=0x00000001
RCR1(0x4700001C)=0x00007f00

XCR2(0x47000020)=0x00000001
XCR1(0x47000024)=0x00000000

SRGR2(0x47000028)=0x00000400
SRGR1(0x4700002C)=0x00000000

MCR2(0x47000030)=0x00000000
MCR1(0x47000034)=0x00000000

PCR(0x47000048)=0x00000001
THRSH2(0x47000090)=0x00000000

THRSH1(0x47000094)=0x00000063
XCCR(0x470000AC)=0x00000000

RCCR(0x470000B0)=0x00000008
IRQEN(0x470000A4)=0x00000000

XBUFFSTAT(0x470000B4)=0x00000080
RBUFFSTAT(0x470000B8)=0x00000000

WAKEUPEN(0x470000A8)=0x00000408

with the above value,i can receive data from FPGA(as master) using poll read.
the EDMA rx call back function below:
static void ti816x_mcbsp_rx_edma_callback(unsigned int lch, u16 ch_status, void *data)
{static int i = 0; printk(" %d ",i++);}

the i value change to ‘1‘ when the edma_start(channel) has been called.and the value i never change again.
the below are the seting for EDMA opt
param.opt = TCINTEN | // Transfer complete interrupt is enabled
                 EDMA_TCC(channel) | // Transfer complete code
               (0 << 8) | // FWID FIFO width is 0:8-bit 1:16-bit 2:32-bit 4:128-bit 5:256-bit
                1; // Source address mode. Constant addressing (CONST) mode
param.src = 0x47000000;
param.a_b_cnt = (1 << 16) | 0x1;

param.dst = buf_phyaddr;
param.src_dst_bidx = 0x00040000;

param.link_bcntrld = (1 << 16) | 0xFFFF ;

param.src_dst_cidx = 0 ;
param.ccnt = 1;

chou tom said:

DRR(0x47000000)=0x00000000

How did you decide that McBSP DRR register is at address of 0x47000000? According to the TRM, it is at address 0x47000100 (0x470000 + 0x100). And all other registers after DDR also has different full addr.

Regards,
Pavel

Hi Pavel
   According to the TRM, it is at address 0x47000100 (0x470000 + 0x100). But i can not configure the McBSP register. e.g., set RCR2 (0x47000118) to 0x1,RCR2 is still a "0" value not changing.
   with the follow setting,i can receiver data from fpga(as master) through poll read DRR(0x47000000) register.
   SYSCON(0x4700008C)=0x00000214

DRR(0x47000000)=0x00000000
DXR(0x47000008)=0x00000000
SPCR2(0x47000010)=0x00000083
SPCR1(0x47000014)=0x00000007
RCR2(0x47000018)=0x00000001
RCR1(0x4700001C)=0x00007f00
XCR2(0x47000020)=0x00000001
XCR1(0x47000024)=0x00000000
SRGR2(0x47000028)=0x00000400
SRGR1(0x4700002C)=0x00000000
MCR2(0x47000030)=0x00000000
MCR1(0x47000034)=0x00000000
PCR(0x47000048)=0x00000001
THRSH2(0x47000090)=0x00000000
THRSH1(0x47000094)=0x00000063
XCCR(0x470000AC)=0x00000000
RCCR(0x470000B0)=0x00000008
IRQEN(0x470000A4)=0x00000000
XBUFFSTAT(0x470000B4)=0x00000080
RBUFFSTAT(0x470000B8)=0x00000000
WAKEUPEN(0x470000A8)=0x00000408

According to the TRM,all register can not configure.

Chou,

Yes, DM816x/AM389x McBSP is at 0x47000000 and registers starts from 0x000, and the first one is DRR. Your register addresses are correct.

What I observe is that you have receiver overrun condition, flagged by the SPCR1[2] RFULL bit. Can you also provide the value of IRQSTATUS/0x470000A0 register? But at the same time you have no data in DRR.

You set the receive threshold to 0x63 (64 bytes), do you have these 64 bytes transferred to the destination address (DDR3 ?) ?

Can you try working in polling mode (no IRQ, no DMA). If everything is correct in polling mode, then your McBSP settings are correct, and we can focus on the EDMA settings.

Regards,
Pavel

Pavel
yes. when working polling mode(no IRQ,no DMA),everything is correct. Each data transferred from FPGA are correct.
but edma not work.
the count value change to ‘1‘ when the edma_start(channel) has been called，and the value never change again.
the follow is some code for edma.

static void ti816x_mcbsp_rx_edma_callback(unsigned int lch, u16 ch_status, void *data)
{
static int count = 0;
printk(" EDMA Callback Count = %d\n ",count++);
}

static int ti81xx_mcbsp_start_edma(struct ti81xx_mcbsp *mcbsp)
{
int ret = 0;
int channel = mcbsp->rx_dma_channel;
int dummy_slot = mcbsp->dummy_param_slot;
unsigned int buf_phyaddr = mcbsp->rx_dma_addr;
unsigned int src_phyaddr = mcbsp->rx_reg; // 0x47000000

struct edmacc_param param;

memset(&param,0x00,sizeof(struct edmacc_param));

/* set to A-synchronized mode acnt*bcnt triger edma*/
param.opt = ITCINTEN |
TCINTEN | // Transfer complete interrupt is enabled
EDMA_TCC(channel) | // Transfer complete code
(2 << 8) | // FWID FIFO width is 0:8-bit 1:16-bit 2:32-bit 4:128-bit 5:256-bit
(0 << 3) | // Set is static. 0:not static ; 1:static
(0 << 1) | // Destination address mode. 0:INCR, 1:CONST
(0 << 0); // Source address mode.0:INCR, 1:CONST

param.src = src_phyaddr;
param.a_b_cnt = (1<< 16) | (4);
param.dst = buf_phyaddr;
param.src_dst_bidx = (4<< 16) | 0x0000; // src_inx = 0 fix src register
param.link_bcntrld = (1<< 16) | 0xFFFF ;
param.src_dst_cidx = 0 ;
param.ccnt = 1;

edma_write_slot(channel, &param);
edma_link(channel,dummy_slot);

edma_write_slot(dummy_slot, &param);
edma_link(dummy_slot,dummy_slot);

ret = edma_start(channel);
if(ret != 0){
printk("Error:Edma start fail!\n") ;
return -1 ;
}
return 0;
}

static int ti816x_mcbsp_edma_setup(struct ti81xx_mcbsp *dev)
{
int r,ret;

r = edma_alloc_channel(dev->rx_dma_sync, ti81xx_mcbsp_rx_edma_callback, dev, EVENTQ_0);
if(r<0){
dev_err(dev->dev,"Unable to request DMA channel for MCBSP RX\n");
goto error_channel;
}

dev->rx_dma_channel = r;
printk(KERN_INFO "McBSP RX EDMA on channel %d(%d)\n",dev->rx_dma_channel,EDMA_CTLR(dev->rx_dma_channel));
edma_clean_channel(dev->rx_dma_channel);

r = edma_alloc_slot(EDMA_CTLR(dev->rx_dma_channel), EDMA_SLOT_ANY);
if(r < 0){
printk(KERN_INFO "Error:Unable alloc slot for channel!\n") ;
goto error_slot ;
}
dev->dummy_param_slot = r;
printk(KERN_INFO "McBSP RX EDMA on slot %d\n",dev->dummy_param_slot);

dev->rx_dma_buf = dma_alloc_coherent(NULL, PAGE_SIZE, &dev->rx_dma_addr,GFP_DMA);
if (NULL == dev->rx_dma_buf){
dev_err(dev->dev, "McBSP RX kzalloc() failed\n");
goto error_alloc_buffer;
}

memset(dev->rx_dma_buf,0,PAGE_SIZE);

ret = ti81xx_mcbsp_start_edma(dev);
if(ret != 0){
printk("Error:call mcbsp_start_edma() fail\n") ;
goto error_start ;
}

printk("EDMA INIT OK!\n");

return 0;
error_start:
dma_free_coherent(NULL, PAGE_SIZE, dev->rx_dma_buf, dev->rx_dma_addr);
error_alloc_buffer:
edma_free_slot(dev->dummy_param_slot) ;
error_slot:
edma_free_channel(dev->rx_dma_channel);
error_channel:
if(dev->rx_dma_buf != NULL)
kfree(dev->rx_dma_buf);
del_timer(&dev->rx_dma_timer);
return -1;
}

Hi Pavel
The McBSP and EDMA is ok. thanks you.
Regards,
Chou

Hi Chou,

I am glad you fix it. Can you please provide some info in brief what was wrong with the EDMA settings?

Regards,
Pavel

Hi Chou,

Can you share your solution for polled mode (or dma) ?

Thank you,
Ran