Tool/software: TI C/C++ Compiler
Hi ,
My hdmi output video from dm8168, will find audio slow down the long period of time use 44.1k, It is strange that 48k is ok. I use CTS_MODE_HW.
Hardware environment: dm8168+rt5642
software environment: dvr_rdk 4.0
dmesg hdmi :
hdmi_acr_mode:CTS_MODE_HW
davinci_hdmi_dai_hw_params:mclk_rate=5644800
omap2_clk_set_rate:clock: set_rate for clock mcbsp_fck to rate 5644800
ti816x_clksel_set_rate:1 pclk->rate=6144000 and rate = 5644800
omap2_clksel_set_rate:
omap2_clksel_round_rate_div:
clock: clksel_round_rate_div: sysclk21_ck target_rate 5644800
_get_clksel_by_parent:
clock: new_div = 2, new_rate = 3072000
ti816x_clksel_set_rate:2 fclk->rate=6144000 and rate = 5644800
ti816x_clksel_set_rate:3 fclk->rate=6144000 and rate=5644800
ti816x_clksel_set_rate:@@start fclk->rate=5644099 and rate=5644800
omap2_clksel_set_rate:
omap2_clksel_round_rate_div:
clock: clksel_round_rate_div: sysclk21_ck target_rate 5644099
_get_clksel_by_parent:
clock: new_div = 1, new_rate = 5644099
_divisor_to_clksel:
_get_clksel_by_parent:
clock: sysclk21_ck: set rate to 5644099
ti816x_clksel_set_rate:@@end fclk->rate=5644099
omap2_clksel_recalc:
_read_divisor:
_clksel_to_divisor:
_get_clksel_by_parent:
clock: sysclk21_ck: recalc'd rate is 5644099 (div 1)
omap2_clksel_recalc:
_read_divisor:
_clksel_to_divisor:
_get_clksel_by_parent:
clock: mcbsp_fck: recalc'd rate is 5644099 (div 1)
omap2_clksel_recalc:
_read_divisor:
_clksel_to_divisor:
_get_clksel_by_parent:
clock: mcbsp_fck: recalc'd rate is 5644099 (div 1)
hdmi_acr_mode:CTS_MODE_HW
CTS mode is HW
Wrapper Enabled...
davinci_pcm_hw_params():
