TMS320DM8168 PCI express Link up failure.
Hi,
We have designed a custom board using the two DM8168, two FPGA all connected to an IDT switch 32NT24B. The IDT upstream port is connected to another idt switch (located on a different board).
Both DM8168's are configured as EP, Gen2.0, 4 lanes.
Occasionally (1 out of 10) on power up, while observing (polling) Debug0 register (according to the suggested EP init sequence) we see that the LTSSM state stays at 0x3 (pooling compliance) and not moving to 0x11 (L0) state.
The below registers were examined and verified, the PCIESS is not at reset ,PLL is locked and values are as expected and the LTSSM is enabled.
All the EP (DM8168's and FPGA's) are fed with same clock generator.
The issue was observed on both DM8168's, although no at the same power up.
PCIE_CFG: 0x48140640: 01C90300
RM_DEFAULT_RSTCTRL: 0x48180b10: 00000003
CM_DEFAULT_PCI_CLKSTCTRL : 0x48180510: 00000102
CM_DEFAULT_PCI_CLKCTRL : 0x48180578: 00000002
Debug 0: 0x51001728: 00AED703
Debug 1: 0x5100172c: 08200000
I have also looked on this post,
https://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/490939
have not tried yet to force Gen1
The device is not hanged, still running , but the link never go up until next power up.
Voltage, clock and reset were measured with scope to find any issue. it seems as require.
Happens at room temperature.
DDR3 testing is performed on every powerup, did not failed.
Can you suggest what to look in order to find any clue for this behavior?