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TMS320DM8168: TMS320DM8168 DIVCLK

Part Number: TMS320DM8168

My customer need to get information regarding the DIVCLK which is a part of the PCIe module.

As he see, DIVCLK is reported as not running, randomly (different for each power up), and without any correlation to our PCIe issue we are currently investigating (Link/Reading from BAR registers).

What can be the cause that it is not running? What are the anticipated outcome of such scenario?

From the documentation they have and from answer they got from the TI E2E they understand that this clock must be enabled and must be running for proper operation of the PCIe module.

They  did not see any explanation for this "div by 5" PLL clock (DIVCLK) in the documentation, only general explanation. is this clock is the 250MHz clock mentioned?
Does jitter on the REFCLK input clock (although it is “locked”, bit[8]LOCK=’1’) can cause the lack of the DIVLCK?

Please help

 

 

 

 

 

 

  • Hi Asi,

    For DM816x HW/SW support, refer to the below e2e post:

    e2e.ti.com/.../426680

    Regards,
    Pavel
  • Asi,

    Please refer to the FAPLL configuration tool attached to the following E2E post.  It will confirm that the settings for the PLLs are valid.  Let us know if the problem still persists when the PLL settings are known to be correct.

    Tom

  • Asi Eizer said:

    As he see, DIVCLK is reported as not running, randomly (different for each power up), and without any correlation to our PCIe issue we are currently investigating (Link/Reading from BAR registers).

    What can be the cause that it is not running?

    I suspect the issue comes from the SERDES 100MHz differential clock. Please double check this clock signal.

    Asi Eizer said:
    They  did not see any explanation for this "div by 5" PLL clock (DIVCLK) in the documentation, only general explanation. is this clock is the 250MHz clock mentioned?

    No, 250MHz is sysclk5 coming from Main PLL.

    Asi Eizer said:
    Does jitter on the REFCLK input clock (although it is “locked”, bit[8]LOCK=’1’) can cause the lack of the DIVLCK?

    I think yes

    Asi,

    This thread is continuation from the below thread:

    The clock scheme of the PCIESS is:

    100MHz differential clock (SERDES_CLKP/AB34 and SERDES_CLKN/AB33) --> PCIe PHY PLL -> PCIe PLL output clock (DIVCLK) -> PCIe Core

    DEV_CLKIN (27MHz) -> Main PLL (FAPLL) -> sysclk5 (250MHz) -> PCIe Core

    The register that is related to PCIe PLL config/status is PCIE_CFG, I do not find any other register. And SERDES_CTRL is used for SERDES clock control. You can also compare SERDES_CTRL register value between working and non-working case.

    If you suspect HW issue, I would suggest you to check:

    - SERDES_CLKP and SERDES_CLKN pins

    - VDDT_PCIE, VDDA_PLL, VDDR_PCIE

    - DM816x datasheet, sections 8.1.8 8.1.8 Power-Supply Decoupling, 8.2.12 PCIe Reset Isolation, 8.3.2 SERDES_CLKN and SERDES_CLKP Input Clock, 9.14 Peripheral Component Interconnect Express (PCIe)

    - DM816x Silicon errata, advisory 2.1.36 SERDES Transit Signals Pass ESD-CDM Up To ±150 V

    - DM816x TRM, sections 17.1.4.4 Clock, Reset, Power Control Logic, 17.2.1 Clock Control, 17.3 Use Case

    The PCIe PHY has an internal that is supplied with a 100 MHz reference clock. The PCIe PHY generates an internal clock for Gen2 and Gen1 operation. It is possible to use several different frequency values for the PHY reference clock. But to comply with the PCIe specifications, it is recommended that the reference clock be 100 MHz with no more than 300 ppm tolerance and be driven as a differential signal.

    It is also recommended that the reference clock be synchronous between the two link partners. To achieve this, a common clock source should be used in the system to provide REFCLK to both ends of each PCIe link.

    If common clock architecture is not used, then the software driver must setup appropriate bits in the PCI Configuration registers to indicate so to the system. The number of training sequences are also increased if reference clock is separate between the peer devices.

    Regards,
    Pavel