Hi,
I have to manage four video stream with a tms320dm8168 DSP using its two Video input port and for each one both port. In this way I send:
- video stream 1 -> VIP 0 Port A
- video stream 2 -> VIP 0 Port B
- video stream 3 -> VIP 1 Port A
- video stream 4 -> VIP 1 Port B
I realized that the (the board in which DSP is mounted was designed by an other person) clock and synchronism signal are connected for VIP 0 Port A, VIP 0 Port B, VIP 1 Port A, but for VIP 1 Port B I have the following status:
- clk -> connected to AT4 pin
- Vsync -> connected to AP9 pin
- Hsync_de -> not connected (it should be connected to AR9 pin)
- Field -> not connected (it should be connected to AU8 pin)
Now I have some questions:
- Should the lack of this signals be a problem for the fouth video stream management?
- Why Hsync and De in VIP 0 Port A, VIP 0 Port B, VIP 1 Port A are separated signals and for VIP 1 Port B are in the same signal and pin? How could I manage this signal/s considering that they are connected to the same pin?
- Is there any user guide or application note explaining this problem?
Thank you
Best regards
Piero Mistretta
