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TI Home » TI E2E Community » Support Forums » Digital Signal Processors (DSP) » DaVinci™ Video Processors » DM816x, C6A816x and AM389x Processors Forum » All Tags » FAPLL
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DaVinci™ Video Processors

Welcome to the DaVinci™ Video Processors Section of the TI E2E Support Community. Ask questions, share knowledge, explore ideas, and help solve problems with fellow engineers. To post a question, click on the forum tab then "New Post".

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FAPLL
  • 675
  • ddr3
  • dm8168
  • PSP
  • u-boot
Related Posts
  • Forum Post: Re: DM8168 set the DDR CLK

    Anil Anil
    Hi Lingyi ying, Change macros at these two locations, then frequency will change to 675MHz. In arch/arm/include/asm/arch-ti81xx/ddr_defs.h file -#define CONFIG_TI816X_DDR3_796 /* Values supported 400,531,675,796 */ +#define CONFIG_TI816X_DDR3_675 /* Values supported 400,531,675,796 */ In arch...
    on Feb 24, 2012
  • Forum Post: Re: DM8168 set the DDR CLK

    Anil Anil
    Lingyi Ying, Could you provide the bootlog (from power-up) and DDR_PLL registers dump from u-boot? TI8168_EVM#md 0x48140440 Regards AnilKumar Please mark this Forum post as answered via the Verify Answer button below if it helps answer your question. Thanks!
    on Feb 27, 2012
  • Forum Post: Re: DM8168 set the DDR CLK

    Anil Anil
    Hi Lingyi Ying, Could you please close this thread by clicking on "Verify Answer"? The same topic is active on other thread http://e2e.ti.com/support/dsp/davinci_digital_media_processors/f/717/t/167359.aspx Regards AnilKumar Please mark this Forum post as answered via the...
    on Feb 27, 2012
  • Forum Post: Re: DM8168 set the DDR CLK

    Anil Anil
    Hi Lingyi Ying, U-Boot 2010.06 (Nov 10 2011 - 19:25:12) This tells me that code was build on November 10th 2011. (First stage) Could you please do only the above modifications, build the u-boot (distclean and re-build) and try once again? You should use both imges are from recent build. ...
    on Feb 27, 2012
  • Forum Post: RE: questions about PLL parameters

    Anil Anil
    Hi Mastupristi, All the values are "AUDIO_*" but not "AUDIO_*+1" If we are not following the limits of the FAPLL then PLL output frequency is not stable and most of the times PLL will not lock. Below example gives you on how the values are used in frequency calculation: MPU...
    on May 4, 2012
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