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Forum Post: DDR pll clock 2 can't pass to SYSCLK10.

KENJI SASAKI

Dear all, I'm developing C6A8168 Boot loader that boot from NOR Flash. Although MAIN,DDR,VIDEO,AUDIO FAPLLs were initialized , SYSCLK10 couldn't get 48MHz. (It's still 27MHz) I confirmed DDR3 clock got 800MHz. Why DDR pll clock2 couldn't pass to SYSCLK10 ? Best regards...

on Sep 16, 2011
Forum Post: DDR_BP bit in DDR PLL Control Register (DDRPLL_CTRL)

Takasugi Hirokazu

Hello, Please teach correct description of DDR_BP (bit2) bit in DDR PLL Control Register (DDRPLL_CTRL) . The latest TRM (SPRUGX9) is described as follow. 0: Normal operation 1: PLL in bypass mode, reference clock driven at output. But the gel file is programmed "1" is Normal operation...

on Oct 11, 2011
Forum Post: Re: Overclock DM8168 ARM and HDVICP clocks.

Anil

Hi Krunal, You can refer section "1.11.3 Flying Adder PLL" in DM8168 TRM for configuring the PLL, make sue that you are not exceeding the supported values. Look at the u-boot code for better understanding the PLL configuration (main_pll_init_ti816x() API in <u-boot source>/board...

on Apr 17, 2012
Forum Post: questions about PLL parameters

mastupristi

I have some questions about PLL parameters. First of all I refer to PLL scheme: The output frequency is given by: The questions are: Range of N? In reference manual is stated that “ N = Multiplier is 9 bits and supported range is 1 to 511 ”, but in register description the field...

on May 3, 2012

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Browse by Tags

Forum Post: DDR pll clock 2 can't pass to SYSCLK10.

Forum Post: DDR_BP bit in DDR PLL Control Register (DDRPLL_CTRL)

Forum Post: Re: Overclock DM8168 ARM and HDVICP clocks.

Forum Post: questions about PLL parameters