DaVinci™ Video Processors

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Related Posts

  • Forum Post: Re: GPMC addressing for C6A816x

    Anuj Aggarwal
    Hi Sweta, I am also trying to achieve the same, however, things are not working well. I am able to write to the slave processor but unable to read from it. Would it be possible for you to share your GPMC register settings? Thanks.
    on Jun 22, 2011

  • Forum Post: TI8168 Burst reading not works correctly : Help us for solve this problem.

    Min Chul KIM
    As announced before, we are using customized TI8168 EVM board. And we have designed customized board reads data from our sensor. sensor reads image for 14bit gray-scaled mono color pixels. From sensor to FPGA, reads pixel information and push it into FIFO. And TI8168 will reads data by using GPMC Synchronous...
    on Jul 21, 2011

  • Forum Post: Running Android On 816X/389X EVM With out IO Expansion board

    valeswararao d
    Hi guys, We are workimg on Sitara evm 8168 and Running android on it. We planing to use the GPMC expansion which is now connected to IO expansion board. Is it possible to run android on it with out IO Expansion board..? Thanks & Regards Valeswara Rao D
    on Sep 12, 2011

  • Forum Post: DM816x/C6A816x/AM389x Evaluation Module ~ NOR Flash

    Swee Sin Ong
    I'm currently designing a expansion board which use the GPMC interface to a Micron's NOR Flash. I can hardly find the reference to use NOR for the Sitara CPU. For the booting purpose, what do u think about this configuration? Asynchronous (this chip only support async, got concern?...
    on Sep 21, 2011

  • Forum Post: Using the DSP's MMU on the 816x

    davedanenberg
    I have a situation where the 816x DSP needs to access external hardware in GPMC space (0x08000000). So within the DSP's virtual space, as I understand it, this could be mapped to 0x11000000 via MMU. I have looked at a relevant TI wiki posting ( http://processors.wiki.ti.com/index.php?title=Talk:DM816x_C6A816x_DEMMU_Setup&oldid...
    on Sep 23, 2011

  • Forum Post: Re: Connecting a large NAND Flash memory device to the GPMC interface of the DM8168

    Galadriel
    Thanks Brad, The device we are looking at is the Micron MT29F8G16 http://download.micron.com/pdf/datasheets/flash/nand/2_4_8gb_nand_m49a.pdf . It is a quad-die stack with two CE# and two R/B# signals. According to the datasheet: CE# and CE2# each control independent 4Gb arrays. CE2# functions...
    on Nov 4, 2011

  • Forum Post: Connecting a large NAND Flash memory device to the GPMC interface of the DM8168

    Galadriel
    Hi, We are currently designing a system based on the DM8168 and we want to use a NAND Flash for memory booting and storing information data. We are planning to use a X16 bus width device and connect it to CS0. The maximum supported memory size of 2Gb per CS of the GPMC does not apply to NAND...
    on Nov 2, 2011

  • Forum Post: How to read/write address & data to/from GPMC while interfacing with NOR memory?

    tan jr
    Hi, I'm using AM389x, and I'm writing a device driver to communicate with FPGA through GPMC. I read through the the Technical Reference Manual : SPRUGX7, found here: http://www.ti.com/general/docs/litabsmultiplefilelist.tsp?literatureNumber=sprugx7 Chapter 9 of this TRM talks about how...
    on Nov 23, 2011

  • Forum Post: GPMC: Cannot access memory on local bus higher than 4K Bytes

    Tri Pham
    Hello, I have a 32K block of NVRAM hanging on the GPMC at CS1. When I tried to access this memory space, I can only go up to 4K Bytes. Address GPMC_A11 to GPMC_A14 stay at 0 and never go high. For experiment, I reconfigured the GPMC_A11-GPMC_A14 as GPIO and set them high. I was able to see the memory...
    on Oct 27, 2011

  • Forum Post: Re: GPMC: Cannot access memory on local bus higher than 4K Bytes

    Jonathan Journo
    Hello, I have encountered the same problem on a DM8148 GPMC interface. the LIMITEDADDRESS also resolved the problem. Thanks a lot Tri Pham. TI guys, please update the TRM.
    on Feb 22, 2012

  • Forum Post: Question on GPMC interface with C6A8168 processor.

    Dinesh Potluru
    Hi From the SPRS680B, it is given C6Integra has 6 Chipselects upto 256MB per chip select pin so cumulatively GPMC has address space of 1536MB. i) Can I connect 1 GB external device(NOR) to the GPMC bus, I think it is not a valid configuration because each chipselect supports 256MB of address space...
    on Mar 12, 2012

  • Forum Post: DM8168 DSP to GPMC Access?

    Jaden Ghylin102047
    Is the DSP in the DM8168 able to access the GPMC directly? If not, what is the method for accessing the GPMC from the DSP? -Jaden
    on Oct 25, 2012

  • Forum Post: RE: How to write a GPMC driver?

    Viet Dinh
    Hi, The best place to start is the DM8168 Technical Reference Manual (TRM) and its driver in the SDK. BR, Viet
    on Mar 14, 2013

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