• Resolved

TMS320DM6437: i2c SCLK remains always low and SDA is always high.

Part Number: TMS320DM6437

I m working on custom board based on tms320dm6437. sclk remains low even after reset (which i see by probing). i m initializing i2c a shown below, 

I2C_ICMDR = 0; // Reset I2C
I2C_ICPSC = 2; // Config prescaler for 27MHz //13
I2C_ICCLKL = 40; // Config clk LOW for 100 kHz //5
I2C_ICCLKH = 40; // Config clk HIGH for 100 kHz //5
I2C_ICMDR |= ICMDR_IRS; // Release I2C from reset

my UART is working fine which is also based on AUX clk, but I2C is not working. what could be the problem??

  • Hi Ateequeur,

    I would suggest you to check your I2C pinmux, clock and power configuration. Refer to the below pointers for details:

    DM6437 datasheet (tms320dm6437.pdf)

    Table 2-22. I2C Terminal Functions
    6.3.4 DM6437 Power and Clock Domains - check PLLC1 settings are correct
    6.3.5 Power and Sleep Controller (PSC) - check registers MDSTAT18 and MDCTL18
    6.12 Inter-Integrated Circuit (I2C)

    See also:

    www.ti.com/.../spru991e.pdf
    www.ti.com/.../spru978e.pdf


    Check also below wiki:

    processors.wiki.ti.com/.../I2C_Tips


    For any detailed software support please contact any of the select partners recommended below.

    e2e.ti.com/.../622094

    Regards,
    Pavel



  • In reply to Pavel Botev:

    1. board is having 27 MHz oscillator.
    2. after PLL initialization
    PLL1 register values:
    PLLCTL 0x00000149 PLL Control Register [Memory Mapped]
    RSTYPE 0x00000001 Reset Type Status Register [Memory Mapped]
    CKEN 0x00000003 PLLDIV Ratio Change Status Register [Memory Mapped]
    CKSTAT 0x0000000B PLLDIV Ratio Change Status Register [Memory Mapped]
    SYSTAT 0x00000007 PLLDIV Ratio Change Status Register [Memory Mapped]

    PLL2 register values:
    PLLCTL 0x00000149 PLL Control Register [Memory Mapped]
    PLLM 0x00000017 PLL Multiplier Register [Memory Mapped]
    PLLSTAT 0x00000006 PLL Controller Status Register [Memory Mapped]
    CKSTAT 0x00000009 PLLDIV Ratio Change Status Register [Memory Mapped]
    SYSTAT 0x00000003 PLLDIV Ratio Change Status Register [Memory Mapped]

    divisor values are also properly selected.(0.2.5)

    3. after PSC initialization
    MDSTAT18 values:
    EMUIHB 0
    EMURST 0
    MCKOUT 1
    MRST 1
    LRSTDONE 1
    LRST 0
    STATE 000011

    MDCTL18 value:
    _RESV 000000000000000000000 Reserved
    EMUIHBIE 0
    EMURSTIE 0
    LRST 0
    _RESV 00000 Reserved
    NEXT 011 Module Next State

    4. After I2C Initialization:
    ICOAR 0x00000000 I2C Own Address Register [Memory Mapped]
    ICIMR 0x00000000 I2C Interrupt Mask Register [Memory Mapped]
    ICSTR 0x00001410 I2C Interrupt Status Register [Memory Mapped]
    ICCLKL 0x00000028 I2C Clock Divider Low Register [Memory Mapped]
    ICCLKH 0x00000028 I2C Clock Divider High Register [Memory Mapped]
    ICCNT 0x00000000 I2C Data Count Register [Memory Mapped]
    ICDRR 0x00000000 I2C Data Receive Register [Memory Mapped]
    ICSAR 0x000003FF I2C Slave Address Register [Memory Mapped]
    ICDXR 0x00000000 I2C Data Transmit Register [Memory Mapped]
    ICMDR 0x00000020 I2C Mode Register [Memory Mapped]
    ICIVR 0x00000000 I2C Interrupt Vector Register [Memory Mapped]
    ICEMDR 0x00000001 I2C Extended Mode Register [Memory Mapped]
    ICPSC 0x00000002 I2C Prescaler Register [Memory Mapped]
    ICPID1 0x00000106 I2C Peripheral ID Register 1 [Memory Mapped]
    ICPID2 0x00000005 I2C Peripheral ID Register 2 [Memory Mapped]

    from all the register values it looks like initialization is done right.

    what else could be the problem??
  • In reply to Pavel Botev:

    whether sclk remains low after reset/ power on with bootloader mode set to 0??
  • In reply to ateequeur rahman:

    ateequeur rahman
    ICMDR 0x00000020 I2C Mode Register [Memory Mapped]

    ICMDR[10] MST = 0, this means DM64x I2C module is in slave mode. In I2C slave mode, this SCL pin is an input. PLL1 values and I2C module prescaler and divider values takes effect on SCL line only when DM64x I2C module is master. When DM64x I2C module is slave, it is waiting for clock to be generated and supplied on SCL pin by the external I2C chip (which is master).

    For more info, check below sections of I2C user guide.

    2.2 Clock Generation

    2.7 Operating Modes - Slave-receiver mode

    2.11.2 Configuring the I2C in Slave Receiver and Transmitter Mode

    Regards,
    Pavel



  • In reply to Pavel Botev:

    as you mentioned ICMDR[10] MST = 0, this means DM64x I2C module is in slave mode. this initialization in our code is done before sending any data on i2c bus.
    thanks for your support, i2c_sclk which was always low become high after we changed the pull up register from 2.2k(recommended) to 1Kohm.
    it was a hardware problem i feel.