DM64x DaVinci Video Processor Forum - Recent Threads

Bug in a certain serial of DM6446: RBL cannot run ubl in nand

Jianjun Zhang — Mon, 17 Jun 2013 11:46:18 GMT

My dm6446 custum board cannot boot from NAND, but another evm is ok . The reason was found after read the disassemble code:

when compare the size of ubl with 14k:

the good one:(RBL1-bin from $NA-06A15FW TMS320DM6446AZWTA)

52f4: e0000c96    mul r0, r6, ip
52f8: e3500b0e    cmp r0, #14336 ; 0x3800
52fc: 8a000080    bhi 0x5504

failed one:(RBL-2.bin from $7C-ICA06HW TM320DM6446BZWT8)
5a4c: e0000a9c    mul r0, ip, sl
5a50: e3500b0e    cmp r0, #14336 ; 0x3800
5a54: 2a000031    bcs 0x5b20;

Obviously bcs is wrong.

What can tell from the SN? ( $NA-06A15FW ,$7C-ICA06HW)

Best Regards,

Zhang Jianjun

(Please visit the site to view this file)

dm6446 hangs

mohammed asif — Mon, 17 Jun 2013 09:57:05 GMT

hi,

please provide solution for this, dm446evm hangs once itstart booting kernel, below is the details,

--------------------------------------------

U-Boot 1.1.3 (Dec 4 2006 - 12:05:38)

U-Boot code: 81080000 -> 81097628 BSS: -> 810A0018
RAM Configuration:
Bank #0: 80000000 256 MB
Flash: 16 MB
In:    serial
Out:   serial
Err:   serial
ARM Clock :- 297MHz
DDR Clock :- 162MHz
Hit any key to stop autoboot: 0
## Booting image at 02050000 ...
   Image Name:   Linux-2.6.10_mvl401-davinci_evm
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    1333196 Bytes = 1.3 MB
   Load Address: 80008000
   Entry Point: 80008000
   Verifying Checksum ... OK
OK

Starting kernel ...

Uncompressing Linux.............................................................
Linux version 2.6.10_mvl401-davinci_evm (xlibrary@scarletoak.sanb.design.ti.com)
(gcc version 3.4.3 (MontaVista 3.4.3-25.0.30.0501131 2005-07-23)) #2 Mon Aug 7
14:58:21 PDT 2006
CPU: ARM926EJ-Sid(wb) [41069265] revision 5 (ARMv5TEJ)
CPU0: D VIVT write-back cache
CPU0: I cache: 16384 bytes, associativity 4, 32 byte lines, 128 sets
CPU0: D cache: 8192 bytes, associativity 4, 32 byte lines, 64 sets
Machine: DaVinci EVM
Memory policy: ECC disabled, Data cache writeback
Built 1 zonelists
Kernel command line: console=ttyS0,115200n8 noinitrd rw ip=dhcp root=/dev/nfs nf
sroot=127.0.0.1:, nolock mem=120M
PID hash table entries: 512 (order: 9, 8192 bytes)
Console: colour dummy device 80x30
Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
Memory: 120MB = 120MB total
Memory: 118784KB available (2271K code, 480K data, 136K init)
Mount-cache hash table entries: 512 (order: 0, 4096 bytes)
CPU: Testing write buffer coherency: ok
spawn_desched_task(00000000)
desched cpu_callback 3/00000000
ksoftirqd started up.
desched cpu_callback 2/00000000
desched thread 0 started up.
NET: Registered protocol family 16
Registering platform device 'musb_hdrc'. Parent at platform
DaVinci I2C DEBUG: 12:15:02 Aug 1 2006
Registering platform device 'i2c'. Parent at platform
usbcore: registered new driver usbfs
usbcore: registered new driver hub
JFFS2 version 2.2. (NAND) (C) 2001-2003 Red Hat, Inc.
yaffs Aug 1 2006 12:14:38 Installing.
Registering platform device 'davincifb.0'. Parent at platform
Setting Up Clocks for DM420 OSD
Console: switching to colour frame buffer device 90x30
fb0: dm_osd0_fb frame buffer device
fb1: dm_vid0_fb frame buffer device
fb2: dm_osd1_fb frame buffer device
fb3: dm_vid1_fb frame buffer device
Serial: 8250/16550 driver $Revision: 1.90 $ 2 ports, IRQ sharing disabled
Registering platform device 'serial8250'. Parent at platform
ttyS0 at MMIO 0x1c20000 (irq = 40) is a 16550A
io scheduler noop registered
io scheduler anticipatory registered
RAMDISK driver initialized: 1 RAM disks of 32768K size 1024 blocksize
Registering platform device 'ti_davinci_emac'. Parent at platform
TI DaVinci EMAC: MAC address is 00:0e:99:02:5a:1a
TI DaVinci EMAC Linux version updated 4.0
TI DaVinci EMAC: Installed 1 instances.
netconsole: not configured, aborting
i2c /dev entries driver
Linux video capture interface: v1.00
Registering platform device 'vpfe.1'. Parent at platform
DaVinci v4l2 capture driver V1.0 loaded
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
ide: Assuming 50MHz system bus speed for PIO modes; override with idebus=xx
hda: TOSHIBA MK4032GAX, ATA DISK drive
elevator: using anticipatory as default io scheduler
ide0 at 0xe10661f0-0xe10661f7,0xe10663f6 on irq 22
hda: max request size: 1024KiB
hda: 78140160 sectors (40007 MB), CHS=16383/255/63
hda: hda1 hda2
ide0: BM-DMA at 0xe1066000-0xe1066007, BIOS settings: hda:pio, hdb:pio
mice: PS/2 mouse device common for all mice
musb_hdrc: version 2.2a/db-0.4.8 [pio] [host] [debug=0]
musb_hdrc: USB Host mode controller at c8060000 using PIO, IRQ 12
musb_hdrc musb_hdrc: new USB bus registered, assigned bus number 1
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
Registering platform device 'davinci-audio.0'. Parent at platform
NET: Registered protocol family 2
IP: routing cache hash table of 512 buckets, 4Kbytes
TCP: Hash tables configured (established 8192 bind 16384)
NET: Registered protocol family 1
NET: Registered protocol family 17
Sending DHCP requests ...... timed out!
IP-Config: Retrying forever (NFS root)...
Sending DHCP requests ...... timed out!
IP-Config: Retrying forever (NFS root)...
Sending DHCP requests ...... timed out!
IP-Config: Retrying forever (NFS root)...
Sending DHCP requests ....

it will hang here.. can you provide me the initial setup env, that i can start fresh..

am3505 and vpfe

David Montoya — Wed, 29 May 2013 19:03:53 GMT

Hello, I want to connect tvp5150am1 with dm6446. It seems that works I see all the registers and it seems that settings are correct, but Linux do not catch any interrupt (VDINT0). When y execute ret = ioctl(capture.capture_fd, VIDIOC_DQBUF, &capture.capture_buf) it does not continue with the code. I see in (SLES213.pdf) to work with ITU BT.656, I need to change only 0x03 register of tvp5150am1, for all the others registers are valid with default values. In the DM6446 I am not sure, I change this registers: 0x50 (REC656) = 0x00000003 0x08 (SYN_MODE) = 0x00032F84 0x14 (HORZ_INFO) = 0x0000059F 0x48 (VDINT) = 0x00010000 0x18 (VERT_START) = 0x00010001 0x1C (VERT_LINES)= 0x000000EF 0x54 (CCDCFG) = 0x00008800 0x24 (HSIZE_OFF) = 0x000005A0 0x28 (SDOFST)= 0x00000249 I'm trying to watch a video of 720 * 480, I don't know how I am doing wrong. I am working with 2.6.37 linux kernel, and with am3505. Thank you David M.

ubl can't run on dm6446 BZWTA

Ray Zheng — Fri, 14 Jun 2013 15:24:48 GMT

I download the newest ubl code from http://arago-project.org/files/releases/davinci-psp_3.x.0.0-r37/sources/flash-utils-davinci.tar.gz, but after flash the bin file to the board, the board can not start with no printing. the cpu we use is TMS320DM6446 BZWTA and flash chip is k9f1208r0c, but it works ok on TMS320DM6446AZWT. I don't know the difference between them, Do I need to modify some code ? so please help me.

dm648 about SGMII to SGMII mode

Jack zhong — Thu, 13 Jun 2013 06:19:49 GMT

I use a customer board in my project.I use dm648 DSP.we do not use PHY instead we use Broadcom switch chip 53115. The DSP is used in SGMII to SGMII mode.But I found the rate of Ethernet can only get about 24Mbps,it's too slow. I use version 1.92 NDK.I have changed something in NDK what I found in wiki.Bellow：

http://processors.wiki.ti.com/wiki/index.php?title=Network_Developers_Kit_FAQ#Q:_How_to_properly_use_the_SMA_connectors_on_my_DM648EVM_board.3F

Q: How to properly use the SMA connectors on my DM648EVM board?

If you intend to use the SMA connectors without a PHY then you must perform the two modifications below:

In the file <evmdm648init.c> lines 102-103, enable the SMA connectors by setting the two variables below to true:

use_SMA_on_port0 = TRUE;
use_SMA_on_port1 = TRUE;

This is the same as setting the parameter CPSW3G_INITPARAM_SPEED0 to 9999u in the device driver include file <cspw3g_init_cfg.h> line 160.

In the device driver source file <cpsw3g_core.c> line 500, prevent the flag pi->TxOn to be reset by commenting out its line:

pi->TxOn = 0;

I want to know where must I  change in order to get  faster rate of Ethernet.   Thanks!

Broken slave SPI when h264 decoder runs

Martin Kolinek — Thu, 13 Jun 2013 21:17:33 GMT

On DM6467, we have the slave end of SPI link to another processor. This link is used to provide network connection, at speed up to 1 megabyte (each way) per second.

When MPEG2 decoder runs on DM6467 (like decoding 1080i), the SPI link works fine. But when H264 decoder runs on DM6467 (even doing easy decode like 480p), the SPI link has lots of errors.

The SPI uses DMA to send/receive bytes from the SPI bus. It seems that H264 grabs DMA resources causing SPI errors. How do we balance H264 and SPI slave to work together? It is ok if H264 has somewhat lower max performance.

YUV422SP to YUV422P on DM6467

Jaden Ghylin102047 — Wed, 12 Jun 2013 16:28:05 GMT

I am working with the JPEG Codec provided via the link below. I am attempting to use the encode demo provided with the DVSDK 3.10 to use the JPEG encoder codec instead of the h264 one.

http://software-dl.ti.com/dsps/dsps_public_sw/codecs/C64XPlus_Video/index_FDS.html

The issue is that the JPEG Codec doen’t support the YUV422SP color space. I need to perform a color space conversion from YUV422SP to YUV422P and I’m trying to figure out the means to do so.

It appears the C6EZAccel libraries can do support this. However, the wiki page for C6EZAccel says that its end of life. I am looking for any suggestions on how to perform the colorspace conversion. Is it ok to use C6EZAccel even though it’s no longer supported?

I’ve also tried using the CCV module in the DMAI, but it appears it can only convert YUV422SP to YUV420SP (semi planar only) and vice versa.

Regards,

-Jaden

TVP70025

Fedoseyev Sergey D. — Tue, 04 Jun 2013 14:00:03 GMT

We want to use TVP70025, but it is now NRND

We need 1-2 composite video inputs and 2 VGA inputs to convert ( selectably ) to digital RGB output ( for transmitting to LCD by LVDS ).

What You can recommended instead TVP70025 (NRND) for industrial temperature ranges of -40 to 85 °C ?

Excuse my English,

Sergey

There is no mtdblockx under /dev

Bo Wang1 — Thu, 13 Jun 2013 11:16:31 GMT

I compiled a new dm646x kernel image for my dm6467 platform. When starting the system using the new kernel image, some logs indicating flash bad eraseblocks show up like the following:

Starting kernel ...

Uncompressing Linux... done, booting the kernel.
Linux version 2.6.37 (root@localhost.localdomain) (gcc version 4.2.0 (MontaVista 4.2.0-16.0.32.0801914 2008-08-30)) #4 PREEMPT Thu Jun 6 13:55:38 CST 2013
CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177
CPU: VIVT data cache, VIVT instruction cache
Machine: DaVinci DM646x EVM
Memory policy: ECC disabled, Data cache writeback
DaVinci dm6467_rev3.x variant 0x1
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 28448
Kernel command line: console=ttyS0,115200n8 noinitrd rw root=/dev/nfs nfsroot=192.168.30.240:/home/comeback/myrootfs,v3,nolock mem=112M eth=00:0E:FF:FF:FF:80 ip=192.168.30.249:192.168.30.240:192.168.30.240
PID hash table entries: 512 (order: -1, 2048 bytes)
Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
Memory: 112MB = 112MB total
Memory: 110140k/110140k available, 4548k reserved, 0K highmem
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
DMA : 0xff000000 - 0xffe00000 ( 14 MB)
vmalloc : 0xc7800000 - 0xfea00000 ( 882 MB)
lowmem : 0xc0000000 - 0xc7000000 ( 112 MB)
modules : 0xbf000000 - 0xc0000000 ( 16 MB)
.init : 0xc0008000 - 0xc0029000 ( 132 kB)
.text : 0xc0029000 - 0xc0323000 (3048 kB)
.data : 0xc0324000 - 0xc0342fa0 ( 124 kB)
SLUB: Genslabs=13, HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Preemptable hierarchical RCU implementation.
RCU-based detection of stalled CPUs is disabled.
Verbose stalled-CPUs detection is disabled.
NR_IRQS:245
Console: colour dummy device 80x30
Calibrating delay loop... 147.86 BogoMIPS (lpj=739328)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
DaVinci: 43 gpio irqs
NET: Registered protocol family 16
MUX: Setting register STSOMUX_DISABLE
PINMUX0 (0x00000000) = 0x00000000 -> 0x00000000
MUX: Setting register STSIMUX_DISABLE
PINMUX0 (0x00000000) = 0x00000000 -> 0x00000000
MUX: Setting register PTSOMUX_DISABLE
PINMUX0 (0x00000000) = 0x00000000 -> 0x00000000
MUX: Setting register PTSIMUX_DISABLE
PINMUX0 (0x00000000) = 0x00000000 -> 0x00000000
bio: create slab <bio-0> at 0
pcf857x: probe of 1-0038 failed with error -121
Switching to clocksource timer0_1
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes)
TCP established hash table entries: 4096 (order: 3, 32768 bytes)
TCP bind hash table entries: 4096 (order: 2, 16384 bytes)
TCP: Hash tables configured (established 4096 bind 4096)
TCP reno registered
UDP hash table entries: 256 (order: 0, 4096 bytes)
UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
NET: Registered protocol family 1
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
msgmni has been set to 215
io scheduler noop registered (default)
Serial: 8250/16550 driver, 3 ports, IRQ sharing disabled
serial8250.0: ttyS0 at MMIO 0x1c20000 (irq = 40) is a ST16654
console [ttyS0] enabled
serial8250.0: ttyS1 at MMIO 0x1c20400 (irq = 41) is a ST16650V2
serial8250.0: ttyS2 at MMIO 0x1c20800 (irq = 42) is a ST16650V2
brd: module loaded
NAND device: Maf ID: 0x20, Chip ID: 0xf1 (ST Micro, )
erasesize: 0x20000, writesize: 2048, oobsize: 64
Scanning device for bad blocks
Bad eraseblock 550 at 0x0000044c0000
Bad eraseblock 551 at 0x0000044e0000
Bad eraseblock 552 at 0x000004500000
Bad eraseblock 553 at 0x000004520000
Bad eraseblock 554 at 0x000004540000
Bad eraseblock 555 at 0x000004560000
Bad eraseblock 556 at 0x000004580000
Bad eraseblock 557 at 0x0000045a0000
Bad eraseblock 558 at 0x0000045c0000

………………………………

Bad eraseblock 798 at 0x0000063c0000
Bad eraseblock 799 at 0x0000063e0000
Bad eraseblock 800 at 0x000006400000
Bad eraseblock 801 at 0x000006420000
Bad eraseblock 803 at 0x000006460000
Creating 5 MTD partitions on "davinci_nand.0":
0x000000000000-0x000000080000 : "bootloader"
0x000000080000-0x0000000a0000 : "params"
0x0000000a0000-0x0000004a0000 : "kernel"
0x0000004a0000-0x0000044a0000 : "filesystem"
0x0000044a0000-0x000008000000 : "yaffs2"
davinci_nand davinci_nand.0: controller rev. 2.2
davinci_mdio davinci_mdio.0: davinci mdio revision 1.4
davinci_mdio davinci_mdio.0: detected phy mask fffffffd
davinci_mdio.0: probed
davinci_mdio davinci_mdio.0: phy[1]: device 0:01, driver ET1011C
dm9000 Ethernet Driver, V1.31
console [netcon0] enabled
netconsole: network logging started
i2c /dev entries driver
TCP cubic registered
NET: Registered protocol family 17
davinci_emac_probe: using random MAC addr: ce:e1:c1:42:2c:74
net eth0: attached PHY driver [ET1011C] (mii_bus:phy_addr=0:01, id=282f014)
IP-Config: Guessing netmask 255.255.255.0
IP-Config: Complete:
device=eth0, addr=192.168.30.249, mask=255.255.255.0, gw=192.168.30.240,
host=192.168.30.249, domain=, nis-domain=(none),
bootserver=192.168.30.240, rootserver=192.168.30.240, rootpath=
PHY: 0:01 - Link is Up - 100/Full
VFS: Mounted root (nfs filesystem) on device 0:12.
Freeing init memory: 132K
starting pid 839, tty '': '/etc/init.d/rcS'

Please press Enter to activate this console.
starting pid 846, tty '/dev/console': '-/bin/sh'

Another thing, when system is booted up, I find that there are only mtdx, but no mtdblockx, under /dev.

/ # ls /dev/mtd*
/dev/mtd0 /dev/mtd1 /dev/mtd2 /dev/mtd3 /dev/mtd4
/dev/mtd0ro /dev/mtd1ro /dev/mtd2ro /dev/mtd3ro /dev/mtd4ro

/ # cat /proc/mtd

dev: size erasesize name
mtd0: 00080000 00020000 "bootloader"
mtd1: 00020000 00020000 "params"
mtd2: 00400000 00020000 "kernel"
mtd3: 04000000 00020000 "filesystem"
mtd4: 03b60000 00020000 "yaffs2"

However, when using the old image, there is nothing special happened. I think it is due to the new kernel image, but I do not know how to fix it.

Regarding DM6467 and DM6467t VPIF

Mayurkumar Akbari — Thu, 13 Jun 2013 06:52:37 GMT

Hi,

We have one 2k x 2k pixel array CMOS sensor. The sensor give 8-bit parallel raw output data.

we want to interface sensor with DM6467 or DM6467t VPIF. I had read the video port interface use guide and as per user guide In 8-bit raw video capturing mode, DM6467 can support upto 2048(H) × 1536(V) pixel array format.

Did DM6467t also can support upto 2048(H) × 1536(V) pixel array format or more?

Best Regards,

Mayur Akbari

Cache Configuration Size

renu — Thu, 13 Jun 2013 06:35:20 GMT

I am working on DM6446 processor.It is having 3 level memory L1,L2 and external memory.

I want to enable cache(L1,L2) of C64X+ processor. For that i've read DM6446 datasheet in which it is written L2 size is 64KB but user guide says you can configure it to 256KB.what does it mean?

I am not clear with memory architecture(specifically size) of C64X+ processor.

C64X+ DSP Megamodule Reference guide says L1P supports 1MB RAM and ROM but datasheet of DM6446 says 32KB only. I am not clear with the size of L1P and L1D.

Kindly help me out

Hough Transofrm for Lines

Xiangfei Dong — Wed, 10 Aug 2011 01:43:58 GMT

Hi ,

When I use the function VLIB_houghLineFromList() in vlib for Hough Transform, I have a question:

I do not konwn how to set the parameters "pEdgeMapList, rhoMaxLength" ? I have read the test code-VLIB_testHough.c, but I still don't understand fully.

If the image is 720*480, how the set the "rhoMaxLenth" value, and how can put the parameters "pEdgeMagList"?

Is there another simple project using VLIB Hough transform for line detection in an image?

My email is : xiangfei.dong@desay-svautomotive.com

Thanks a lot.

I am looking forward to your reply as soon as possible.

64xx AAC Encoder

jie chen — Sun, 09 Jun 2013 03:16:43 GMT

I am just getting started with DM6467.I found aac decoder as the dsp client in the dvsdk but I couldn't find the aac encoder.Could anyone help me?

spliting bilingual analog stream into two different languages

prathamesh ghanekar1 — Mon, 10 Jun 2013 08:50:32 GMT

Hello,

In our setup, we are working on Davinci DM6467 based board.Kernel running underneath is 2.6.32-rc2.For DSP side applications, we are using DVSDK_3_10_00_16.

In the application, analog signal is read from FPGA over HPI port. A LIVE analog TV signal broadcast is fed as an input to the board. The signal is further demodulated and decoded using ak4141 stereo demodulator.

Now, Sometimes, Bilingual programs are broadcast on the Television.

In the application ,ioctl is called which detects the bilingual/stereo/mono channels etc.

After determining that the channel being broadcast is a bilingual channel, i am looking forward to separating the left and right channel data and derive the 2 languages data separately(1 in left channel, and other in the right).

Firstly, is that possible..??

Later, i generate left and right channel audio samples in the .aac format, and expect that both would have different languages when bilingual program is on air.Am i going in the right direction??

Currently, with the following code, i am getting both aac files to be of the same language.

Following is what i have done to separate the left and right channel data from the data read over HPI port.

The code goes something like this:

/*L-Channel data*/

LchBuffHndArr = Buffer_create(ANALOG_BUFFER_SIZE, &bAttrs);

hpiBufPhyAddr.val1 = (unsigned int)Buffer_getPhysicalPtr(LchBuffHndArr);

/*R-channel data*/

RchBuffHndArr = Buffer_create(ANALOG_BUFFER_SIZE, &bAttrs);

hpiBufPhyAddr.val2 = (unsigned int)Buffer_getPhysicalPtr(RchBuffHndArr);

ioctl(fd_Fpga,

CAPTURE_I2S_DATA /*macro from davinci_hpi driver*/,

(void*)&hpiBufPhyAddr);

//this ioctl actually reads data from the FPGA over hpi port.

And, then read the data using user space pointers.

/*Read L-Channel data*/

LchDataBuf = (char*) Buffer_getUserPtr(LchBuffHndArr);

What can be done to retrieve 2 separate language's audio samples?

Thanks and regards,

Prathamesh Ghanekar

Driver for DM6467T TVP5158 dvsdk3.10

Mark Kewley — Mon, 10 Jun 2013 17:49:10 GMT

Hello all,

I already know that TI did not make an updated driver for the dvsdk3_10 for the DM6467T and TVP5158. Has anyone else made this driver and are they willing to share their driver with me?

Thanks,

- Mark

How to boot dm6446 from SD card

Aly Khalifa — Sun, 02 Jun 2013 14:18:05 GMT

Can anyone help me to boot my dm6446evm kit from the SD card

DM6446 interruptions

David Montoya — Wed, 29 May 2013 11:47:12 GMT

Hello,

I have am3505 processor with video input. I see in documentation "The VPFE controller can generate three interrupts: CCDC_VD0_INT, CCDC_VD1_INT, and
CCDC_VD2_INT. The CCDC_VD0_INT and CCDC_VD1_INT interrupts occur relative to the VD pulse ... The CCDC_VD2_INT interrupt always occurs at the falling edge of the VDIN_WEN signal".

My question is, when video format is BT.646 we do not have any VD pulse (if I am not wrong), how VPFE controller interrupts or what is the interruption?

Thank you.

David M.

!!!!Question about SOFTWARE PIPELINE INFORMATION

Ferdinand — Sat, 08 Jun 2013 02:19:15 GMT

hi:

Recently I optimized a specific function.But I was puzzled with SOFTWARE PIPELINE INFORMATION.

Why Aft Optimization Wasted more time than Bef optimization????In SOFTWARE PIPELINE INFORMATION

Bef optimization, ii = 33 Schedule found with 1 iterations in parallel.But Aft optimization ,

ii = 10 Schedule found with 5 iterations in parallel. why Aft optimization run slower than Bef optimization?

Bef Optimization:

;*----------------------------------------------------------------------------*

;* SOFTWARE PIPELINE INFORMATION

;* Loop source line : 166

;* Loop opening brace source line : 167

;* Loop closing brace source line : 186

;* Known Minimum Trip Count : 1

;* Known Max Trip Count Factor : 1

;* Loop Carried Dependency Bound(^) : 32

;* Unpartitioned Resource Bound : 9

;* Partitioned Resource Bound(*) : 11

;* Resource Partition:

;* A-side B-side

;* .L units 3 5

;* .S units 5 7

;* .D units 3 5

;* .M units 4 6

;* .X cross paths 8 10

;* .T address paths 2 4

;* Long read paths 0 0

;* Long write paths 0 0

;* Logical ops (.LS) 0 0 (.L or .S unit)

;* Addition ops (.LSD) 7 16 (.L or .S or .D unit)

;* Bound(.L .S .LS) 4 6

;* Bound(.L .S .D .LS .LSD) 6 11*

;* Searching for software pipeline schedule at ...

;* ii = 32 Did not find schedule

;* ii = 33 Schedule found with 1 iterations in parallel

Aft optimization:

;*----------------------------------------------------------------------------*

;* SOFTWARE PIPELINE INFORMATION

;* Loop source line : 166

;* Loop opening brace source line : 167

;* Loop closing brace source line : 186

;* Known Minimum Trip Count : 1

;* Known Max Trip Count Factor : 1

;* Loop Carried Dependency Bound(^) : 5

;* Unpartitioned Resource Bound : 9

;* Partitioned Resource Bound(*) : 10

;* Resource Partition:

;* A-side B-side

;* .L units 5 3

;* .S units 6 5

;* .D units 5 3

;* .M units 3 7

;* .X cross paths 7 10*

;* .T address paths 2 4

;* Long read paths 0 0

;* Long write paths 0 0

;* Logical ops (.LS) 0 0 (.L or .S unit)

;* Addition ops (.LSD) 10 13 (.L or .S or .D unit)

;* Bound(.L .S .LS) 6 4

;* Bound(.L .S .D .LS .LSD) 9 8

;* Searching for software pipeline schedule at ...

;* ii = 10 Schedule found with 5 iterations in parallel

Best Regards!

LSP to PSP help for DM6467T TVP5158 driver

Mark Kewley — Tue, 11 Jun 2013 13:13:21 GMT

Hello,

I am currently trying to update this driver:

http://e2e.ti.com/cfs-file.ashx/__key/telligent-evolution-components-attachments/00-376-01-00-00-14-55-33/mcvip_5F00_tvp5158_5F00_v010013_5F00_20100211.zip

which was posted in this post from Viet:

http://e2e.ti.com/support/data_converters/videoconverters/f/376/t/41768.aspx

For some odd reason TI still has not made an update to this for the newer Linux kernel and dvsdk 3_10. My question is in the two make files one located in

/mcvip_tvp5158/build/Makefile

======================================BEGIN MAKEFILE CODE=====================================

# (c) Texas Instruments

include RULES.MK
include $(BASE_DIR)/COMMON_HEADER.MK


exe:
   make depend
   make libs
   make -fMAKEFILE.MK -C$(BASE_DIR)/../test/mcvip/src MODULE=mcvip_test exe
   make -fMAKEFILE.MK -C$(BASE_DIR)/../test/i2crw MODULE=i2crw exe
   make -fMAKEFILE.MK -C$(BASE_DIR)/../test/dma MODULE=dma_test exe
   make install

libs:
   make -fMAKEFILE.MK -C$(BASE_DIR)/../osa/src MODULE=osa $(TARGET)
   make -fMAKEFILE.MK -C$(BASE_DIR)/../drv/usermod/src MODULE=drv $(TARGET)
   # FOLLOWING UPDATE 6-10-13 make -C$(BASE_DIR)/../drv/kermod/build $(TARGET)
   make -fMAKEFILE.MK -C$(BASE_DIR)/../mcvip/src MODULE=mcvip $(TARGET)
   make -fMAKEFILE.MK -C$(BASE_DIR)/../test/mcvip/src MODULE=mcvip_test $(TARGET)
   #These look to be commented out on the dm365 from online, try if it comes up
#   make -fMAKEFILE.MK -C$(BASE_DIR)/../test/i2crw MODULE=i2crw $(TARGET)
   make -fMAKEFILE.MK -C$(BASE_DIR)/../test/dma MODULE=dma_test $(TARGET)

all:
   make clean
   make exe

clean:
   make libs TARGET=clean
   -rm -f $(EXE_BASE_DIR)/*.out
   -rm -f $(TARGET_FS_DIR)/*.out

depend:
   -mkdir -p $(EXE_BASE_DIR)
   -mkdir -p $(TARGET_FS_DIR)
   make libs TARGET=depend

install:
   make libs TARGET=install
   cp $(EXE_BASE_DIR)/*.out   $(TARGET_FS_DIR)
   cp $(EXE_BASE_DIR)/*.sh   $(TARGET_FS_DIR)

dvsdkbuild:
   make -C$(DVSDK_BASE_DIR) $(DVSDK_TARGET)

dvsdk:
   make dvsdkbuild DVSDK_TARGET=
   make dvsdkbuild DVSDK_TARGET=install

dvsdkclean:
   make dvsdkbuild DVSDK_TARGET=clean

dvsdkall:
   make dvsdkclean
   make dvsdk

lspbuild:
   make -C$(KERNELDIR) ARCH=arm CROSS_COMPILE=arm_v5t_le- $(TARGET)

lspcfg:
   make lspbuild TARGET=davinci_dm646x_defconfig
   make lspbuild TARGET=checksetconfig

lsp:
   make lspcfg
   make lspbuild TARGET=uImage
   cp $(KERNELDIR)/arch/arm/boot/uImage $(TFTP_HOME)/uImage_DM6467

lspall:
   make lspclean
   make lsp

lspclean:
   make lspbuild TARGET=clean

nfsreset:
   /usr/sbin/exportfs -av
   /sbin/service nfs restart

sys:
   make lsp
   make dvsdk
   make

sysclean:
   make lspclean
   make dvsdkclean
   make clean

sysall:
   make lspall
   make dvsdkall
   make all

.PHONY : lsp lspcfg lspall lspbuild install clean depend all app mods nfsreset lspclean allall dvsdk dvsdkall dvsdkclean dvsdkbuild

======================================END MAKEFILE CODE=====================================

What I have highlighted in bold is where I have the most errors. I believe this is from MontaVista's developer kit. Is there an equivalent for the Code Composer's/PSP? Or should I download MontaVista? If so how?

The second makefile is in:

/mcvip_tvp5158/lsp_files/lsp_patch_1GHZ/Makefile

======================================BEGIN MAKEFILE CODE=====================================

LSP_PATCH=.
LSP_BACKUP_DIR=lsp_backup

LSP_DIR=/home/user/lsp_1_30_82/montavista/pro/devkit/lsp/ti-davinci/linux-2.6.10_mvl401_LSP_01_30_00_082

#/ked/DM6467_1GHZ/lsp/ti-davinci
TVP5158_PATCH=$(LSP_PATCH)/TVP5158_Support

backup:
   -mkdir $(LSP_BACKUP_DIR)
   -mkdir $(LSP_BACKUP_DIR)/Common
   -mkdir $(LSP_BACKUP_DIR)/THS8200_Display_Support
   -mkdir $(LSP_BACKUP_DIR)/TVP5158_Support
   cp $(LSP_DIR)/include/media/davinci/ths8200_encoder.h $(LSP_BACKUP_DIR)/THS8200_Display_Support/.
   cp $(LSP_DIR)/drivers/media/video/davinci/ths8200_encoder.c $(LSP_BACKUP_DIR)/THS8200_Display_Support/.
   cp $(LSP_DIR)/drivers/media/video/davinci/davinci_enc_mngr.c $(LSP_BACKUP_DIR)/THS8200_Display_Support/.
   cp $(LSP_DIR)/drivers/media/video/Kconfig $(LSP_BACKUP_DIR)/THS8200_Display_Support/.
   cp $(LSP_DIR)/arch/arm/mach-davinci/video_hdevm.c $(LSP_BACKUP_DIR)/Common/.
   cp $(LSP_DIR)/drivers/media/video/davinci/davincihd_display.c $(LSP_BACKUP_DIR)/Common/.
   cp $(LSP_DIR)/drivers/i2c/busses/i2c-davinci.c $(LSP_BACKUP_DIR)/Common/.
   cp $(LSP_DIR)/include/asm-arm/arch-davinci/timex.h $(LSP_BACKUP_DIR)/Common/.
   cp $(LSP_DIR)/drivers/media/video/davinci/vpif.c $(LSP_BACKUP_DIR)/TVP5158_Support/.
   cp $(LSP_DIR)/sound/oss/dm646x/audio_controller.c $(LSP_BACKUP_DIR)/TVP5158_Support/.
   cp $(LSP_DIR)/drivers/media/video/davinci/davincihd_capture.c $(LSP_BACKUP_DIR)/TVP5158_Support/.
   cp $(LSP_DIR)/sound/oss/dm646x/audio_controller.h $(LSP_BACKUP_DIR)/TVP5158_Support/.
   cp $(LSP_DIR)/sound/oss/dm646x/davinci-aic32.h $(LSP_BACKUP_DIR)/TVP5158_Support/.
   cp $(LSP_DIR)/sound/oss/dm646x/davinci-audio-aic32.c $(LSP_BACKUP_DIR)/TVP5158_Support/.
   cp $(LSP_DIR)/arch/arm/mach-davinci/mcasp.c $(LSP_BACKUP_DIR)/TVP5158_Support/.
   cp $(LSP_DIR)/include/asm-arm/arch-davinci/mcasp.h $(LSP_BACKUP_DIR)/TVP5158_Support/.

patch: backup
   cp $(LSP_PATCH)/Common/timex.h $(LSP_DIR)/include/asm-arm/arch-davinci/timex.h
   cp $(LSP_PATCH)/Common/i2c-davinci.c $(LSP_DIR)/drivers/i2c/busses/i2c-davinci.c
   cp $(LSP_PATCH)/Common/davincihd_display.c $(LSP_DIR)/drivers/media/video/davinci/davincihd_display.c
   cp $(LSP_PATCH)/Common/video_hdevm.c $(LSP_DIR)/arch/arm/mach-davinci/video_hdevm.c
   cp $(LSP_PATCH)/THS8200_Display_Support/Kconfig $(LSP_DIR)/drivers/media/video/Kconfig
   cp $(LSP_PATCH)/THS8200_Display_Support/davinci_enc_mngr.c $(LSP_DIR)/drivers/media/video/davinci/davinci_enc_mngr.c
   cp $(LSP_PATCH)/THS8200_Display_Support/ths8200_encoder.c $(LSP_DIR)/drivers/media/video/davinci/ths8200_encoder.c
   cp $(LSP_PATCH)/THS8200_Display_Support/ths8200_encoder.h $(LSP_DIR)/include/media/davinci/ths8200_encoder.h
   cp $(TVP5158_PATCH)/davincihd_capture.c $(LSP_DIR)/drivers/media/video/davinci/davincihd_capture.c
   cp $(TVP5158_PATCH)/vpif.c $(LSP_DIR)/drivers/media/video/davinci/vpif.c
   cp $(TVP5158_PATCH)/audio_controller.c $(LSP_DIR)/sound/oss/dm646x/audio_controller.c
   cp $(TVP5158_PATCH)/audio_controller.h $(LSP_DIR)/sound/oss/dm646x/audio_controller.h
   cp $(TVP5158_PATCH)/davinci-aic32.h $(LSP_DIR)/sound/oss/dm646x/davinci-aic32.h
   cp $(TVP5158_PATCH)/davinci-audio-aic32.c $(LSP_DIR)/sound/oss/dm646x/davinci-audio-aic32.c
   cp $(TVP5158_PATCH)/mcasp.c $(LSP_DIR)/arch/arm/mach-davinci/mcasp.c
   cp $(TVP5158_PATCH)/mcasp.h $(LSP_DIR)/include/asm-arm/arch-davinci/mcasp.h

======================================END MAKEFILE CODE======================================

This Makefile is used for the tvp5158 patch, what I have in bold is what is troubling me. Again, is there an equivalent way of doing this through PSP? If so how would I do so? Or should I download the LSP/MontaVista? Again, how would I do so?

Thanks for all the help!

- Mark

Reg. Increase in Jitter when NDK library is used with TI DM642 DSP processor

Kandhasamy Rajasekaran — Sun, 09 Jun 2013 17:16:01 GMT

Hi All,

I have been using TI DM642 processor along with a set of libraries that TI has provided.

The following is the experiment that I did to understand the behavior of TI DSP and NDK library.

Whenever signal "X" to DSP is raised from low to high, a HWI function is invoked in my program, which in turn will set signal "Y" high for 5 microseconds (this time is not a concern here) and set it low afterwards. I have set up a mechanism through which signal "X" will be turned high and low at a speed of 1Khz (Speed is not the concern here). When i measured it in Oscilloscope by tapping the signals "X" and "Y", I saw a jitter of 250 nano seconds between rise in 'X" and start of rise of signal "Y".

I used NDK library for TCP communication with a GUI that we have built. We used functions like NC_SystemOpen, NC_NetStart to configure TCP protocol stack and run it separately in a task. In a separate thread we establish a connection with GUI and sends some data regularly. When we configured NDK scheduler to be in high priority and interrupt mode then the jitter rates went up to 50 microseconds. When we configured it to Low priority and polling method, it came down to 15 microseconds approximately.

Why is there a increase in jitter rate when NDK library is used? What is NDK library doing to it? Is there a way to stop it? Or is there anything wrong that I am doing in configuration? Has anybody undergone this and achieved better results?

Any sort of idea or help is appreciated.

Thanks

Kandhasamy

DSP BIOS in EVM6437

Himanshu Adhikari — Mon, 10 Jun 2013 13:23:05 GMT

hi....

I am using EVMDM6437 evaluation module in which I successfully run UART receive firmware using DSP BIOS.But when I made firmware for UART transmit,it does not work ,i.e., the interrupt is not generated. I used uart in FIFO mode.

However,when I run uart in non FIFO mode in case of UART transmit , the interrupt is generated,and the program goes to the defined subroutine. I used HWI4 of BIOS and mapped to interrupt no.84 of UART interrupt in DM6437.So please help me with a possible solution to use UART transmit in FIFO mode.

Also please tell if I want to use UART transmit and receive sumultaneously in the same project, whether I have to make two different threads for both of them?

Lucas Kanade optic flow

Vestaproman — Fri, 26 Nov 2010 15:24:59 GMT

Hello every one,

I have got a question about how to use the "VLIB_trackFeaturesLucasKanade_7x7" function.

I have two successive images of 160 x 160 pixels from a video camera.

I detect the good features to track using VLIB function : "VLIB_harrisScore_7x7"

That work fine.

But after I want to track the points using the Lucas-Kanade method and I same results in outx and x, and outy and y.

But when I try with OPENCV on PC computer I use the Harris VLIB function for corner detection and Lucas-Kanade OPENCV function that work fine.

In the OPENCV function, they use a pyramid image.

Did anyone has an idea how to use correctly the "VLIB_trackFeaturesLucasKanade_7x7" function

Thanks a lot

Jérôme

Can we use the intrinsic in dm6446?

nn3351 — Tue, 05 May 2009 16:14:14 GMT

Hi, I have a question:

Our algorithm has some codes with " intrinsic ". After we compiler it on linux (dm6446), it shows

" warning: implicit declaration of function `_amem8_const' "

Does it work? I think it doesn't work. Whether we should include any header file? Thanks.

UBL_DM646x_NAND_675_324.zip

Mark Kewley — Thu, 06 Jun 2013 15:44:27 GMT

Hi,

I am following the TVP5158 EVM User's guide and under section 7.2.1 it says to "Unzip the UBL_DM646x_NAND_675_324.zip archive file onto the PC's local hard drive."

I can not find this .zip file anywhere?? Any help or a link would be great!

- Mark

Reset I2C bus using SCL and SDA pin that in new linux kernel I2C buss code

Dhvani Patel1 — Thu, 16 May 2013 09:31:32 GMT

I want to reset I2C bus of DM6467 whenever there is timeout during i2c data transfer. in new kernel 3.9 there is support added using

static void i2c_recover_bus(struct davinci_i2c_dev *dev) function. in drivers/i2c/busses/i2c-davinci.c file

But when i am using this function for my DM6467 device at that time it is giving me error of sdl and scl pin number.

Here is some code snippet from kernel 3.9

1 ) arch/arm/mach-davinci/board-dm646x-evm.c

     static struct davinci_i2c_platform_data i2c_pdata = {

          .bus_freq       = 100 /* kHz */,

          .bus_delay      = 0 /* usec */,

};

2) arch/arm/mach-davinci/board-dm355-evm.c

  static struct davinci_i2c_platform_data i2c_pdata = {

     .bus_freq       = 20 /* kHz */,

     .bus_delay      = 100 /* usec */,

    .sda_pin        = 44,

    .scl_pin        = 43,

};

3) arch/arm/mach-davinci/board-dm355-evm.c

static struct davinci_i2c_platform_data i2c_pdata = {
.bus_freq = 400 /* kHz */,
.bus_delay = 0 /* usec */,
.sda_pin = 15,
.scl_pin = 14,
};

Here can any one give me some idea about sda_pin and scl_pin for DM646x processor , in kernel code there is already sda_pin and scl_pin for dm644x and dm355-evm board .

Please provide me some information about sda_pin and scl_pin.

Thanks in Advanced,

-regards,

Dhvani Patel