Hi
I am setting up a system to capture video thru' DM648 VPORT.
Using pspdrivers 1.10 and CCS 4.2.
My application is unable to open the vport driver. FVID_create() always fails.
There is something wrong fundamentally in my approach. I added all the necessay statically built libs in the PSP drivers to my capture application. Attached is my tcf file. Any help would be appreciated.
utils.loadPlatform("ti.platforms.evmDM648");
/* The following DSP/BIOS Features are enabled. */
bios.enableRealTimeAnalysis(prog);
bios.enableRtdx(prog);
bios.enableTskManager(prog);
utils.importFile("common.tci");
// !GRAPHICAL_CONFIG_TOOL_SCRIPT_INSERT_POINT!
bios.enableMemoryHeaps(prog);
bios.tskNdkStackTest = bios.TSK.create("mainTask");
bios.tskNdkStackTest.fxn = prog.extern("task");
bios.tskNdkStackTest.stackSize = 0x1000;
bios.tskNdkStackTest.priority = 0x5;
// Check that stack size is big enough for the application
if (bios.MEM.STACKSIZE < 0x1000) {
bios.MEM.STACKSIZE += 0x1000;
}
/* BIOS Timer Fix - This can be removed later */
bios.GBL.CLKOUT = 726.0000;
bios.CLK.SPECIFYRATE = 1;
bios.CLK.INPUTCLK = 121.0000;
bios.GBL.CALLUSERINITFXN = 1;
bios.GBL.USERINITFXN = prog.extern("evmdm648_init");
// Move all sections to DDR2
bios.setMemCodeSections(prog, prog.get("DDR2"));
bios.setMemDataHeapSections(prog, prog.get("DDR2"));
bios.setMemDataNoHeapSections(prog, prog.get("DDR2"));
/* Enable ECM Handler */
bios.ECM.ENABLE = 1;
bios.HWI.instance("HWI_INT7").interruptSelectNumber = 0;
bios.HWI.instance("HWI_INT8").interruptSelectNumber = 1;
bios.HWI.instance("HWI_INT9").interruptSelectNumber = 2;
bios.HWI.instance("HWI_INT10").interruptSelectNumber = 3;
/* Enable Cache */
bios.GBL.C64PLUSMAR224to255 = 0x0000ffff;
bios.MEM.instance("IRAM").len = 0x00040000;
bios.GBL.C64PLUSL2CFG = "256k";
/*
* ======== I2C Configuration ========
*/
bios.UDEV.create("I2C0");
bios.UDEV.instance("I2C0").fxnTableType = "IOM_Fxns";
//bios.UDEV.instance("I2C0").initFxn = prog.extern("I2C_INIT");
bios.UDEV.instance("I2C0").params = prog.extern("I2C_devParams");
bios.UDEV.instance("I2C0").fxnTable = prog.extern("I2CMD_FXNS");
// Board specific settings
// Create a heap in external memory
bios.DDR2.len = 0x08000000;
bios.DDR2.createHeap = true;
bios.DDR2.heapSize = 0x01000000;
bios.setMemDataHeapSections(prog, prog.get("DDR2"));
// Remove IRAM since we've set L2 to be cache
bios.IRAM.destroy();
/*
* ======== VPORT Configuration ========
*/
//bios.VP0CAPTURE = bios.UDEV.create("VP0CAPTURE");
//bios.VP0CAPTURE.fxnTable = prog.extern("VPORTCAP_Fxns");
//bios.VP0CAPTURE.fxnTableType = "IOM_Fxns";
//bios.VP0CAPTURE.params = prog.extern("vCapParamsPort");
//bios.VP0CAPTURE.deviceId = 0x00;
//bios.VP1CAPTURE = bios.UDEV.create("VP1CAPTURE");
//bios.VP1CAPTURE.fxnTable = prog.extern("VPORTCAP_Fxns");
//bios.VP1CAPTURE.fxnTableType = "IOM_Fxns";
//bios.VP1CAPTURE.params = prog.extern("vCapParamsPort");
//bios.VP1CAPTURE.deviceId = 0x01;
//bios.VP2CAPTURE = bios.UDEV.create("VP2CAPTURE");
//bios.VP2CAPTURE.fxnTable = prog.extern("VPORTCAP_Fxns");
//bios.VP2CAPTURE.fxnTableType = "IOM_Fxns";
//bios.VP2CAPTURE.params = prog.extern("vCapParamsPort");
//bios.VP2CAPTURE.deviceId = 0x02;
//bios.VP3CAPTURE = bios.UDEV.create("VP3CAPTURE");
//bios.VP3CAPTURE.fxnTable = prog.extern("VPORTCAP_Fxns");
//bios.VP3CAPTURE.fxnTableType = "IOM_Fxns";
//bios.VP3CAPTURE.params = prog.extern("vCapParamsPort");
//bios.VP3CAPTURE.deviceId = 0x03;
//bios.VP4CAPTURE = bios.UDEV.create("VP4CAPTURE");
//bios.VP4CAPTURE.fxnTable = prog.extern("VPORTCAP_Fxns");
//bios.VP4CAPTURE.fxnTableType = "IOM_Fxns";
//bios.VP4CAPTURE.params = prog.extern("vCapParamsPort");
//bios.VP4CAPTURE.deviceId = 0x04;
/* Video Port Init function which does the LPSC and Pin Muxing requirements */
//bios.VP0CAPTURE.initFxn = prog.extern("VPORT0_init");
//bios.VP1DISPLAY.initFxn = prog.extern("VPORT1_init");
//bios.VP3DISPLAY.initFxn = prog.extern("VPORT3_init");
//bios.VP4CAPTURE.initFxn = prog.extern("VPORT4_init");
bios.VP0CAPTURE = bios.UDEV.create("VPHCAPTURE");
bios.VP0CAPTURE.fxnTable = prog.extern("VPORTCAP_Fxns");
bios.VP0CAPTURE.fxnTableType = "IOM_Fxns";
bios.VP0CAPTURE.params = prog.extern("vCapParamsPortHD");
bios.VP0CAPTURE.deviceId = 0x08;
bios.VP0CAPTURE.initFxn = prog.extern("VPORT0_init");
bios.VP0CAPTURE = bios.UDEV.create("VP0CAPTURE");
bios.VP0CAPTURE.fxnTable = prog.extern("VPORTCAP_Fxns");
bios.VP0CAPTURE.fxnTableType = "IOM_Fxns";
bios.VP0CAPTURE.params = prog.extern("vCapParamsPort");
bios.VP0CAPTURE.deviceId = 0x00;
bios.VP0CAPTURE.initFxn = prog.extern("VPORT0_init");
bios.VP2CAPTURE = bios.UDEV.create("VP2CAPTURE");
bios.VP2CAPTURE.fxnTable = prog.extern("VPORTCAP_Fxns");
bios.VP2CAPTURE.fxnTableType = "IOM_Fxns";
bios.VP2CAPTURE.params = prog.extern("vCapParamsPort");
bios.VP2CAPTURE.deviceId = 0x02;
bios.VP2CAPTURE.initFxn = prog.extern("VPORT2_init");
bios.VP3CAPTURE = bios.UDEV.create("VP3CAPTURE");
bios.VP3CAPTURE.fxnTable = prog.extern("VPORTCAP_Fxns");
bios.VP3CAPTURE.fxnTableType = "IOM_Fxns";
bios.VP3CAPTURE.params = prog.extern("vCapParamsPort");
bios.VP3CAPTURE.deviceId = 0x03;
bios.VP3CAPTURE.initFxn = prog.extern("VPORT3_init");
bios.VP4CAPTURE = bios.UDEV.create("VP4CAPTURE");
bios.VP4CAPTURE.fxnTable = prog.extern("VPORTCAP_Fxns");
bios.VP4CAPTURE.fxnTableType = "IOM_Fxns";
bios.VP4CAPTURE.params = prog.extern("vCapParamsPort");
bios.VP4CAPTURE.deviceId = 0x04;
bios.VP4CAPTURE.initFxn = prog.extern("VPORT4_init");
/* Task for Video test */
//bios.TSK.create("mainTask");
//bios.TSK.instance("mainTask").priority = 2;
//bios.TSK.instance("mainTask").fxn = prog.extern("task");
//bios.TSK.instance("mainTask").stackMemSeg = prog.get("DDR2");
//bios.TSK.instance("mainTask").comment = "RAW Loop Back Task";
//bios.TSK.instance("mainTask").stackSize = 4096;
bios.LOG.create("DVTEvent_Log");
bios.LOG.instance("DVTEvent_Log").bufSeg = prog.get("IRAM");
bios.LOG.instance("DVTEvent_Log").bufLen = 8192;
bios.LOG.instance("DVTEvent_Log").comment = "DVT";
bios.MEM.instance("DDR2").heapSize = 0x00200000;
bios.MEM.instance("DDR2").heapSize = 0x01000000;
//bios.TSK.instance("tskNdkStackTest").priority = 3;
bios.GBL.CLKOUT = 891.0000;
bios.GBL.C64PLUSL1PCFG = "0k";
bios.GBL.C64PLUSL1DCFG = "0k";
bios.GBL.C64PLUSL2CFG = "0k";
bios.GBL.C64PLUSL1PCFG = "32k";
bios.GBL.C64PLUSL1DCFG = "32k";
bios.GBL.C64PLUSL2CFG = "256k";
bios.MEM.instance("DDR2").heapSize = 0x04000000;
bios.MEM.instance("DDR2").heapSize = 0x01000000;
bios.MEM.instance("DDR2").heapSize = 0x02000000;
bios.MEM.instance("DDR2").heapSize = 0x01000000;
bios.MEM.instance("DDR2").heapSize = 0x02000000;
bios.MEM.STACKSIZE = 0x20000;
bios.MEM.instance("DDR2").heapSize = 0x01000000;
bios.MEM.instance("DDR2").heapSize = 0x02000000;
bios.MEM.instance("DDR2").heapSize = 0x03000000;
bios.UDEV.create("VP1CAPTURE");
bios.UDEV.instance("VP1CAPTURE").fxnTableType = "IOM_Fxns";
bios.UDEV.instance("VP1CAPTURE").initFxn = prog.extern("VPORT0_init");
bios.UDEV.instance("VP1CAPTURE").fxnTable = prog.extern("VPORTCAP_Fxns");
bios.UDEV.instance("VP1CAPTURE").params = prog.extern("vCapParamsPort");
bios.UDEV.instance("VP1CAPTURE").initFxn = prog.extern("VPORT1_init");
bios.UDEV.instance("VP1CAPTURE").deviceId = 1;
bios.UDEV.instance("VP1CAPTURE").initFxn = prog.extern("VPORT2_init");
bios.UDEV.instance("VP1CAPTURE").deviceId = 2;
bios.UDEV.instance("VP1CAPTURE").destroy();
bios.MEM.STACKSIZE = 0x40000;
bios.GBL.SPECIFYRTSLIB = 0;
bios.MEM.instance("DDR2").heapSize = 0x04000000;
bios.GBL.SPECIFYRTSLIB = 0;
bios.HST.HOSTLINKTYPE = "NONE";
bios.GBL.ENABLEALLTRC = 0;
bios.GBL.INSTRUMENTED = 0;
bios.GBL.ENABLEINST = 0;
bios.GBL.USERINITFXN = prog.extern("evmdm648_init");
bios.MEM.STACKSIZE = 0x4000;
//bios.TSK.instance("tskNdkStackTest").priority = 5;
bios.GBL.CLKIN = 33000;
bios.CLK.INPUTCLK = 148.5000;
bios.GBL.CLKOUT = 924.0000;
bios.CLK.INPUTCLK = 154.0000;
//bios.TSK.instance("tskNdkStackTest").fxn = prog.extern("task");
bios.MEM.instance("IBUF").destroy();
bios.MEM.instance("IBUF_FULL").destroy();
bios.MEM.create("L2SRAM");
bios.MEM.instance("L2SRAM").base = 0x00a40000;
bios.MEM.instance("L2SRAM").len = 0x00040000;
bios.MEM.instance("L2SRAM").createHeap = 0;
bios.MEM.instance("L2SRAM").space = "code/data";
bios.MEM.instance("CACHE_L2").base = 0x00a00000;
bios.MEM.instance("SEQPMEM").destroy();
bios.MEM.instance("SEQDMEM").destroy();
bios.MEM.instance("IMXCMDMEM").destroy();
bios.MEM.instance("IWMEM").destroy();
bios.MEM.ENABLELOADADDR = 1;
bios.MEM.ENABLELOADADDR = 0;
bios.MEM.STACKSEG = prog.get("L2SRAM");
bios.MEM.BSSSEG = prog.get("DDR2");
bios.MEM.STACKSIZE = 0x10000;
bios.MEM.CIOSEG = prog.get("L2SRAM");
bios.MEM.instance("CIO").destroy();
bios.MEM.CONSTSEG = prog.get("L2SRAM");
bios.PRD.USECLK = 1;
//bios.SWI.instance("PRD_swi").priority = 6;
//bios.TSK.instance("tskNdkStackTest").priority = 6;
//bios.TSK.instance("tskNdkStackTest").priority = 5;
//bios.TSK.instance("tskNdkStackTest").order = 1;
bios.TSK.instance("TSK_idle").order = 2;
//bios.TSK.instance("tskNdkStackTest").priority = 4;
// !GRAPHICAL_CONFIG_TOOL_SCRIPT_INSERT_POINT!
prog.gen();
/*
* ======== common.tci ========
* Custom settings that apply to all the DM648 Examples.
*
*/
/* Enable BIOS Instrumentation and RTA. */
bios.enableRealTimeAnalysis(prog);
bios.enableRtdx(prog);
/* Increase the buffer size of the LOG_system LOG object */
bios.LOG.instance("LOG_system").bufLen = 1024;
bios.LOG_system.logType = "circular";
/* A LOG object named "trace" used by some examples: */
bios.LOG.create("trace");
bios.LOG.instance("trace").bufLen = 4096;
/* Enable BIOS heaps and task scheduler */
bios.enableTskManager(prog);
bios.enableMemoryHeaps(prog);
/* Setup heaps in DDR2 and L2 RAM */
utils.getProgObjs(prog, bios);
var vDDR2 = prog.module("MEM").instance("DDR2");
vDDR2.createHeap = true;
vDDR2.name = "DDR2";
vDDR2.heapSize = 0x04000000;
/*
* Enable a heap in the L2 RAM,
* and define the label for DSKT2 or DMAN3 heap usage
*
* H.264 Encoder needs 64Kb of internal memory.
*/
bios.IRAM.createHeap = true;
bios.IRAM.enableHeapLabel = true;
bios.IRAM["heapLabel"] = prog.extern("L2SRAM");
bios.IRAM.heapSize = 0x10000; // 64KB
bios.IRAM.len = 0x00060000;
/* GBL configuration */
bios.GBL.C64PLUSCONFIGURE = true;
bios.GBL.C64PLUSL1PCFG = "32k";
bios.GBL.C64PLUSL1DCFG = "32k";
bios.GBL.C64PLUSL2CFG = "256k"; //L2 is actually 1408K as per the memory map.
// Make 256MB (0x10000000) DDR2 Cacheable from DDR2's base: 0xE0000000
bios.GBL.C64PLUSMAR224to255 = 0x0000ffff;
//bios.GBL.C64PLUSMAR224to255 = 0x00000000; // Disables cache.
/* set all BIOS data and code sections to be in DDR */
bios.setMemDataHeapSections(prog, vDDR2);
bios.setMemDataNoHeapSections(prog, vDDR2);
bios.setMemCodeSections(prog, vDDR2);
/* Ensure these are in external memory: */
bios.MEM.MALLOCSEG = vDDR2;
bios.MEM.BIOSOBJSEG = vDDR2;
bios.TSK.STACKSEG = vDDR2;
/* Make global stack size large enough for all examples: */
bios.MEM.STACKSIZE = 0x12000;
/* Additional sections required by the H.264 encoder link.xdt file: */
// Conditionally destroy IMCOP:
// BIOS 5.31.07 platform file does not have IMCOP, but XDC 2.94 does, so
// we must test here until XDC 2.95 is released with platform files
// (used by codec engine) in sync with BIOS 5.31.07 platform files.
var imcop = bios.MEM.instance("IMCOP");
if (imcop != null) {
imcop.destroy();
}
bios.MEM.create("IBUF");
bios.MEM.instance("IBUF").comment = "Image Coprocessor Memory";
bios.MEM.instance("IBUF").len = 0x00020000;
bios.MEM.instance("IBUF").base = 0x00100000;
bios.MEM.instance("IBUF").createHeap = 0;
bios.MEM.instance("IBUF").len = 0x00002000;
bios.MEM.create("IBUF_FULL");
bios.MEM.instance("IBUF_FULL").comment = "Image Coprocessor Memory";
bios.MEM.instance("IBUF_FULL").base = 0x00104000;
bios.MEM.instance("IBUF_FULL").len = 0x00004000;
bios.MEM.instance("IBUF_FULL").createHeap = 0;
bios.MEM.create("IWMEM");
bios.MEM.instance("IWMEM").comment = "IWMEM";
bios.MEM.instance("IWMEM").base = 0x00108000;
bios.MEM.instance("IWMEM").len = 0x00008000;
bios.MEM.instance("IWMEM").createHeap = 0;
bios.MEM.create("SEQPMEM");
bios.MEM.instance("SEQPMEM").comment = "SEQPMEM";
bios.MEM.instance("SEQPMEM").base = 0x00110000;
bios.MEM.instance("SEQPMEM").len = 0x00001000;
bios.MEM.instance("SEQPMEM").createHeap = 0;
bios.MEM.create("IMXCMDMEM");
bios.MEM.instance("IMXCMDMEM").comment = "IMXCMDMEM";
bios.MEM.instance("IMXCMDMEM").base = 0x00114000;
bios.MEM.instance("IMXCMDMEM").len = 0x00002000;
bios.MEM.instance("IMXCMDMEM").createHeap = 0;
bios.MEM.create("SEQDMEM");
bios.MEM.instance("SEQDMEM").comment = "SEQDMEM";
bios.MEM.instance("SEQDMEM").base = 0x0209f400;
bios.MEM.instance("SEQDMEM").len = 0x00000400;
bios.MEM.instance("SEQDMEM").createHeap = 0;
/*
* TEMP: create a CIO section for the H.264 enc/dec link.xdt files, and to
* avoid the C STDIO CCS prefetch issue (to be fixed in CCS 3.3 SR2).
*/
bios.MEM.instance("DDR2").len = 0x0ff00000;
bios.MEM.create("CIO");
bios.MEM.instance("CIO").comment = "CIO";
bios.MEM.instance("CIO").base = 0xeff00000;
bios.MEM.instance("CIO").len = 0x00100000;
bios.MEM.instance("CIO").createHeap = 0;
bios.MEM.instance("CIO").space = "code/data";
bios.MEM.CIOSEG = prog.get("CIO");
Regards
JK
