I want to control EDMA transfer priority for requests coming from PCI master. $2.2.3 in SPRA994 says that "The priority level of these transfers is determined by the TR control register (TRCTL), located in the master peripheral register set." Indeed, $15.3.15 in SPRU581c gives a detailed description of TRCTL register. However, it also says that "See the device-specific datasheet for the memory address of these registers" but I cannot find the address of that register in any available documentation, in particular, in SPRUEL4b which describes PCI module for DM648.
Is it possible to change the default value of PCI master priority queue level and the total number of outstanding requests for DM648?