Hi,everyone:
I have a problem in use QDMA in DM6467. I used the DVSDK3.0 edmak.ko to do the test.
I picked some of the main code as shown below. I checked the registers and PRAM, There is no problem, and IPR register can latched interrupt,
but the content in srcBuf2 still had not changed. I don't know what's the problem,I have spent a long time on it. Help me !~!
Thanks in advance!
My code :
#define EDMA_QDMA_CHANNEL_0 0
#define EDMA_NUM_QDMACH 8
struct EDMA_channelParams
{
int channelNO;
unsigned short acnt;
unsigned short bcnt;
unsigned short ccnt;
signed short srcBidx;
signed short destBidx;
signed short srcCidx;
signed short destCidx;
unsigned long srcAddr;
unsigned long destAddr;
};
void qdmaTest(int channel,
void (*callback)(unsigned channel, u16 ch_status, void *data),
void *data,
enum dma_event_q eventq_no,
struct EDMA_channelParams dma_params)
{
int j;
unsigned int mask;
if ((channel >= EDMA_QDMA_CHANNEL_0 && channel < EDMA_QDMA_CHANNEL_0 + EDMA_NUM_QDMACH) ||
EDMA_QDMA_CHANNEL_ANY == channel) {
edma_or_array2(0, EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f)); //enable EDMA shadow region 0 access
edma_or_array(0, EDMA_QRAE, 0, 1 << channel); //enable QDMA shadow region 0 access
j = channel >> 5;
mask = (1 << (channel & 0x1f));
edma_write_array(0, EDMA_QEMCR, j, mask); //clear QEMR register
edma_write(0, EDMA_CCERRCLR, 0x13f); //clear CCERR register
edma_shadow0_write(0, SH_ICR, 0xFFFFFFFF); //clear IPR register
edma_shadow0_write(0, SH_QEECR, mask); //clear QEER register
edma_shadow0_write(0, SH_QSECR, mask); //clear QSER register
edma_parm_write(0, PARM_LINK_BCNTRLD, 96, 0x0000FFFF); // I used PRAM entry 96 to associated with QDMA channel 0;
edma_parm_write(0, PARM_OPT, 96, (0x1 << 3 | 0x1 << 20 | 0x1 << 21)); // set STATIC TCINTEN ITCINTEN
edma_shadow0_write(0, SH_QEESR, 0x1); // enable the QEER for QDMA channel 0;
edma_write_array(0, EDMA_QDCHMAP, 0, (96 << 5) | TRWORD); // PRAM entry 96 associated with QDMA channel 0,and set trigger word
map_qdmach_queue(0, channel, eventq_no); //Set the QDMAQNUM register
edma_write(0, EDMA_QUEPRI, 0x00000111); //Set priority register
if (callback) //install the Interrupt callback
setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, 0), callback, data);
edma_parm_write(0, PARM_SRC, 96, dma_params.srcAddr);
edma_parm_write(0, PARM_DST, 96, dma_params.destAddr);
edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, 96, 0xffff0000, dma_params.srcBidx);
edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, 96, 0xffff0000, dma_params.srcCidx);
edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, 96, 0x0000ffff, dma_params.destBidx << 16);
edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, 96, 0x0000ffff, dma_params.destCidx << 16);
edma_parm_write(0, PARM_A_B_CNT, 96, (dma_params.bcnt << 16) | dma_params.acnt);
edma_parm_write(0, PARM_CCNT, 96, dma_params.ccnt); //set ccnt ,start the transfer.
}
return ;
}
int main( )
{
char strBuf1[512] = {1};
char strBuf2[512] = {0};
struct EDMA_channelParams edmaParams;
edmaParams.channelNO = 0; //Just use QDMA0 for test
edmaParams.acnt = 512;
edmaParams.bcnt = 1;
edmaParams.ccnt = 1;
edmaParams.srcBidx = 0;
edmaParams.destBidx = 0;
edmaParams.srcCidx = 0;
edmaParams.destCidx = 0;
edmaParams.srcAddr = (unsigned int)strBuf1;
edmaParams.destAddr =(unsigned int)strBuf2;
qdmaTest(0, NULL ,NULL, 0, edmaParams);
usleep(10 * 1000 * 1000);
printf("%d, %d\n", strBuf2[0],strBuf2[1]);
return 0;
}