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loading of DSP out file from ARM

Hi,

  i am facing an issue loading DSP bin file from ARM.The following .cmd DSP file, i am using  

-c                                                                 
-stack  0x100                            
-heap   0x100                      
-lrts6400.lib                          
 
MEMORY
{
    SDRAM:    origin = 0x877034C0, len = 0x15000
    L2RAM:    origin = 0x118024C0, len = 0x10000
    L1DRAM:    origin = 0x11F04000, len = 0xc000
}
 

SECTIONS
{
    .text        >   SDRAM
    .switch     >   L2RAM
    .cinit      >   L2RAM
    .const        >   L2RAM
    .bss         >   L2RAM
    .data       >   L2RAM
    .stack      >   L1DRAM
    .sysmem     >   L1DRAM
    .far        >   L2RAM
    .pinit      >   L2RAM
    .template   >   L2RAM
    .cio        >   L2RAM
    .csl_vect   >    L2RAM
    RTS_CODE     >     L2RAM  
    VpssData    >      L2RAM
}

Wen i use the following .cmd dsp file , dsp bin loading and running is successful

-c                                                                 
-stack  0x100                            
-heap   0x100                      
-lrts6400.lib                          
 
MEMORY
{
    SDRAM:    origin = 0x877034C0, len = 0x15000
    //L2RAM:    origin = 0x118024C0, len = 0x10000
    //L1DRAM:    origin = 0x11F04000, len = 0xc000
}
 

SECTIONS
{
    .text        >   SDRAM
    .switch     >   SDRAM
    .cinit      >   SDRAM
    .const        >   SDRAM
    .bss         >   SDRAM
    .data       >   SDRAM
    .stack      >   SDRAM
    .sysmem     >   SDRAM
    .far        >   SDRAM
    .pinit      >   SDRAM
    .template   >   SDRAM
    .cio        >   SDRAM
    .csl_vect   >    SDRAM
    RTS_CODE     >     SDRAM  
    VpssData    >      SDRAM
}

     So, please help why in first case , the dsp bin loading and running is not successful.

Thanking you,

Pulla Rao Chilakala,

Bharat Electronics Limited ,Central Research Labs,

Bangalore


 

  • Hi Pulla,

    What is the exact processor name are you using ?

    What are you trying to do ?

    Why did you use "SDRAM" for .text section alone and rest of the sections are "L1/L2" ?

    SECTIONS
    {
        .text        >   SDRAM
        .switch     >   L2RAM
        .cinit      >   L2RAM
        .const        >   L2RAM
        .bss         >   L2RAM
        .data       >   L2RAM
        .stack      >   L1DRAM
        .sysmem     >   L1DRAM
        .far        >   L2RAM
        .pinit      >   L2RAM
        .template   >   L2RAM
        .cio        >   L2RAM
        .csl_vect   >    L2RAM
        RTS_CODE     >     L2RAM  
        VpssData    >      L2RAM
    }