1. Purpose:
My DM6467 chip frequency of 729mhz, but my software from the EVM board,
so the actual operating frequency of ARM core 297mhz, DSP core 529mhz.
So I want to change my software so that the operating frequency of ARM core364.5mhz, DSP core 729mhz.
2, I modified as follows:
1)In the ubl of platfrom.asm, add the following code:
LDR R6, PLL_1_PLLM ;/* PLL_2 multiplier control register */
MOV R2, #0x1a ;/* */
STR R2, [R6] ;/* 27MHz * 27 = 729MHz */
2)Modify u-boot configuration, as follows:
#define CONFIG_SYS_CLK_FREQ 364500000 /* Arm Clock frequency */
#define CFG_TIMERBASE 0x01C21400 /* use timer 0 */
#define CFG_HZ 182250000 /* Timer Input clock freq */
3, the phenomenon:
1), the actual operating frequency of ARM core is 364.5mhz, the start information as follows:
NAND device: Manufacturer ID: 0x20, Chip ID: 0xf1 (ST Micro NAND 128MiB 3,3V 8-bit)
128 MiB
In: serial
Out: serial
Err: serial
ARM Clock :- 364.5MHz
DDR Clock :- 297MHz
2)、nand flash error, while the root file system mount error, print information as follows:
Scanning device for bad blocks
Bad eraseblock 0 at 0x00000000
Bad eraseblock 1 at 0x00020000
Bad eraseblock 2 at 0x00040000
……
Bad eraseblock 1020 at 0x07f80000
Bad eraseblock 1021 at 0x07fa0000
Bad eraseblock 1022 at 0x07fc0000
Bad eraseblock 1023 at 0x07fe0000
No filesystem could mount root, tried: cramfs
Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(31,3)
3)、If I reduce the frequency, such as the PLL_1_PLLM modified to 0x14 or 0x13, the system can boot properly.
4.questions:
1) In order to let my board to work at 729mhz frequency, what should I modify it?
2) According to my configuration, I just put the frequency increases, have not changed anything else, why NAND flash will not work it? But I reduce the frequency it is working properly.