mcr instruction not getting compiles with ti-4.9 compiler

Hi,

 we are working on the DM6446 davinci processor. in our's ethernet driver, we are using the packet descriptors to transmit and receive the packets.we got emac_send/recv codes from u-boot. in that they are doing the invalidate_dcache_range by executing the below code

while (start < stop) {
                asm volatile("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(start));
                start += CONFIG_SYS_CACHELINE_SIZE;
        }

if i compile this code in CCS , its giving assembly errors, i think ti-5.1 compiler doesn't support these way of calling the assembly from c code.

based on the ti forum help i changed this code to below one, but still i am getting errors, main problem is with ": : "r"(start))";    (dont know  how to pass start value, and its use)

while (start < stop) {
                asm (" mcr p15, 0, #0, c7, c6, #1\n" : : "r"(start));
                start += CONFIG_SYS_CACHELINE_SIZE;
        }

i also tried to keep this assembly code in .asm file , still am getting assembly error.

so can you please correct my code.

regards

Kishore