Dear Sir,
I am facing the problem DDR3 in DM8168 processor. we are using only one chip select.
Getting the data as 0x0 instead of data. can you mail me what could be problem?
/*
* DDR3 EMIF Paramters set for 400 MHz Clock Frequency
*/
#define EMIF_TIM1_DDR3_400 0x0CCCE524
#define EMIF_TIM2_DDR3_400 0x30308023
#define EMIF_TIM3_DDR3_400 0x009F82CF
#define EMIF_SDREF_DDR3_400 0x10000C30
#define EMIF_SDCFG_DDR3_400 0x62A41032 // 32 bit ddr3, CL=11, 8 banks, CWL=8 10 bit column, 2 CS
#define EMIF_PHYCFG_DDR3_400 0x0000030B // local odt = 3, read latency = 11 (max = 12, min=6
#define WR_DQS_RATIO_BYTE_LANE3 ((0x4a << 10) | 0x4a)
#define WR_DQS_RATIO_BYTE_LANE2 ((0x4a << 10) | 0x4a)
#define WR_DQS_RATIO_BYTE_LANE1 ((0x4a << 10) | 0x4a)
#define WR_DQS_RATIO_BYTE_LANE0 ((0x4a << 10) | 0x4a)
#define WR_DATA_RATIO_BYTE_LANE3 (((0x4a + 0x40) << 10) | (0x4a + 0x40))
#define WR_DATA_RATIO_BYTE_LANE2 (((0x4a + 0x40) << 10) | (0x4a + 0x40))
#define WR_DATA_RATIO_BYTE_LANE1 (((0x4a + 0x40) << 10) | (0x4a + 0x40))
#define WR_DATA_RATIO_BYTE_LANE0 (((0x4a + 0x40) << 10) | (0x4a + 0x40))
#define RD_DQS_RATIO ((0x40 << 10) | 0x40)
#define DQS_GATE_BYTE_LANE0 ((0x13a << 10) | 0x13a)
#define DQS_GATE_BYTE_LANE1 ((0x13a << 10) | 0x13a)
#define DQS_GATE_BYTE_LANE2 ((0x13a << 10) | 0x13a)
#define DQS_GATE_BYTE_LANE3 ((0x13a << 10) | 0x13a)
#define DDRPHY_CONFIG_BASE ((emif == 0) ? 0x48198000 : 0x4819a000)
Data at 80000000 7fffffff 7fffffff
Data at 80000004 7ffffffb 7ffffffb
Data at 80000008 7ffffff7 7ffffff7
Data at 8000000c 7ffffff3 7ffffff3
Data at 80000010 7fffffef 7fffffef
Data at 80000014 7fffffeb 7fffffeb
Data at 80000018 7fffffe7 7fffffe7
Data at 8000001c 7fffffe3 7fffffe3
Data at 80000020 7fffffdf 7fffffdf
Data at 80000024 7fffffdb 7fffffdb
Data at 80000028 7fffffd7 7fffffd7
Data at 8000002c 7fffffd3 7fffffd3
Data at 80000030 7fffffcf 7fffffcf
Data at 80000034 7fffffcb 7fffffcb
Data at 80000038 7fffffc7 7fffffc7
Data at 8000003c 7fffffc3 7fffffc3
Data at 80000040 7fffffbf 7fffffbf
Data at 80000044 7fffffbb 7fffffbb
Data at 80000048 7fffffb7 7fffffb7
Data at 8000004c 7fffffb3 7fffffb3
Data at 80000050 7fffffaf 7fffffaf
Data at 80000054 7fffffab 7fffffab
Data at 80000058 7fffffa7 7fffffa7
Data at 8000005c 7fffffa3 7fffffa3
Data at 80000060 7fffff9f 7fffff9f
Data at 80000064 7fffff9b 7fffff9b
Data at 80000068 7fffff97 7fffff97
Data at 8000006c 7fffff93 7fffff93
Data at 80000070 7fffff8f 7fffff8f
Data at 80000074 7fffff8b 7fffff8b
Data at 80000078 7fffff87 7fffff87
Data at 8000007c 7fffff83 7fffff83
Data at 80000080 00000000 7fffff7f
Error at 80000080
Data at 80000084 00000000 7fffff7b
Error at 80000084
Data at 80000088 00000000 7fffff77
Error at 80000088
Data at 8000008c 00000000 7fffff73
Error at 8000008c
Data at 80000090 00000000 7fffff6f
Error at 80000090
Data at 80000094 00000000 7fffff6b
Error at 80000094
Data at 80000098 00000000 7fffff67
Error at 80000098
Regards
Balaji
