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DM6446 USB_DM and USB_DP voltage during USB PHY Initialization

Guru 15510 points

Hi,

I have a question about DM6446 USB PHY initialization.

At the end of USB PHY initialization when setting USBPHY_CTL.PHYPDWN bit
from 1(powerd off) to 0(powered on), USB_DP and USB_DM voltage goes to about 1[V] for a moment
and then drop to about 100[mV]. Pleas see the atached file which I capture the signal from oscilloscope.

Is this a specification of DM6446 USB?
And will this affect to USB enumeration and data communication?

This issue are seen at DM6446EVM and my customer's board.

best regards,
g.f.

DM6446EVM USB_DM and USB_DP voltage .pdf

  • Hi,

    We are working on this and will get back to you shortly.

    Thanks & regards,
    Sivaraj K
  • g.f.

    Can we please have more detail on the setup when this condition happens? Is it happening consistently? Is the USB cable plugged into a USB port with 5V VBUS on? Does the SESSION bit of the DEVCTL register set to 1 or clear to 0?

    Thanks

    David

  • Hi David,

    Thank you for the reply.

    This will occur when I just configure the USBPHY_CTL register.
    For example, after connecting DM6446EVM to CCS and GEL(for the EVM) runs,
    USBPHY_CTL register's value is 0x000000C7(default value).
    Then I only configure the the bit2"OSCPDWN" and bit0"PHYPWDN" to zero,
    the D+ and D- lines goes to about 1V.
    In this case oneside of USB cable are connected to EVM USB A connector and
    nothing are connected to otherside of cable.

    If cable are not connected to the EVM, D+/D- goes to about 3V after clearing the above register bits.

    In either case, this will happens always after configuring the bit0"PHYPWDN" to zero.

    best regards,
    g.f.
  • g,f

    Can you please explain why with no cable attached, you see 3V on DP/DM, but with cable attached, you see 1V on DP/DM?

    When PHYPWDN bit set to 0, can you check the USB 1.8V and 3.3V? Do they come up the same time or one of them come up first and the other one come up next?

    Thanks

    David

  • Hi David,

    Thank you for the reply.

    >Can you please explain why with no cable attached,
    >you see 3V on DP/DM, but with cable attached, you see 1V on DP/DM?

    I don't know. But I guess maybe it's impedance of USB cable.

    >When PHYPWDN bit set to 0, can you check the USB 1.8V and 3.3V?
    >Do they come up the same time or one of them come up first and the other one come up next?

    USB 1.8V and 3.3V are already supplied  when I configure the PHYPWDN bit to 0.
    I will attach the file.

    By the way, I checked the USB 1.8V and 3.3V power sequence.
    When I power On the EVM, 3.3V come up first and then 1.8V come up next.

    best regard,
    g.f.

    DM6446EVM_USB Voltage.pdf

  • g.f.

    The cable impedance is 90ohm +/15%, but I don't see how the cable would impact the voltage of DP/DM.

    Since the glitch eventually goes away, I don't see this as an issue. Have you tried to connect DM6446 to a host and verified it works?

    Thanks
    David
  • Hi David,

    Thank you for the reply.

    Actually this question is from my key customer.

    They are having connection issue with the host PC.
    Right now, they are not thinking that this connection issue depends to DM6446,
    because other USB device also can't connect to host PC.
    But the glitch on DP/DM apply only when connecting DM6446 USB device.
    (There are no glitch apply when connecting other USB device to host)
    So, they are asking that will this glitch will affect to connecting to host and
    is it a spec of DM6446?

    I need to answer to my customer.
    So, can I answer to my customer that this glitch is spec of DM6446 but
    it will not affect to connection issue because this glitch will come up
    during USB PHY initialization which is done before USB enumeration
    and it eventually goes away?

    best regards,
    g.f.
  • g.f

    I thought the glitch happens when DM6446 is not connected to host PC, please confirm this. 

    When connecting to the host PC, do they see the glitch? If not, then the glitch is part of the PHY initialization which is done before the enumeration, so it should not impact the enumeration.

    Thanks

    David

  • Hi David,

    This issue(glitch) will occur whether the Host PC are connected.
    So, it seem that this glitch is part of PHY initialization.

    Can I answer to my customer that this glitch is device(DM6446) characteristic?

    best regards,
    g.f.
  • g.f

    What happens when you set bit 2 to 0 first, wait for awhile, and then set bit 0 to 0?

    Thanks

    David

  • Hi David,

    Thank you for the reply.

    >What happens when you set bit 2 to 0 first, wait for awhile, and then set bit 0 to 0?
    I tried and it was same. D+/D- goes up to 3V or 1V.

    best regards,
    g.f.
  • g.f.

    Would you please try one more experiment of setting bit 2 to 1, and set bit 0 to 0? Can you also please set bit 6 and 7 to 1?

    Is the test condition the same when D+/D- goes up to 3V and 1V?

    Thanks
    David
  • Hi David,

    Thank you for the reply.

    >Would you please try one more experiment of setting bit 2 to 1, and set bit 0 to 0? Can you also please set bit 6 and 7 to 1?
    I try this test and the result was that after D+/D- lines goes up to 1V(or3V), it never drop down to about 0V.
    D+ and D- lines are keeping 1V(or 3V).
    I will attach the captured signal, so please take a look.

    And the test condition is the same when D+/D- goes up to 1V and 3V.DM6446 USB DM_DP signal.pdf

    best regards,
    g.f.

  • Hi David,

    I have additional information.
    I wroted the infromation in the attached file(page. 3 and page.4).
    Can you please take a look the file.

    By the way, the page.1 of the file is the result of setting USBPHY_CTL bit6,7 to one, bit2 to one
    and then clear bit0 to zero. And this is which I attached previously.

    best regards,
    g.f.

    DM6446 USB DM_DP rev2.pdf

  • g.f

    Thanks for the additional information. After step 5, if you keep bit 2 to 0, and just set bit 0 to 1 and then 0, do you see this glitch?

    Thanks

    David

  • Hi David,

    Thank you for the reply.
    I set the bit as you mentioned above and checked the D+/D- line. I can see this glitch.
    D+/D- line goes up to 1V(or 3V) and after about 15us it droped down to about 100mV.

    best regards,
    g.f.
  • g.f

    It looks like the glitch comes from the PHY being powered on the first time, but I do not see this as a functional issue.

    Thanks

    David

  • Hi David,

    Thank you for the reply.

    I need to answer to my customer that this glitch are spec of DM6446 or not.
    This glitch will always occur when powering up the USB PHY.
    So, can I tell my customer that this is spec of DM6446 but this will not cause an issue?
    The reason for "not cause an issue" is that this glitch only occur when powering on the PHY
    and this is before USB enumeration. So, this glitch doesn't affect against USB connection problem.

    best regards,
    g.f.
  • g.f.

    From the data collected so far, I agree with what you said. It is still better to understand why we can't enumerate with the host. Is it just one host or multiple hosts not able to enumerate?

    Thanks
    David
  • Hi David,

    Thank you for the reply.

    Okay, I will answer to the customer that this is spec of DM6446 USB and it does not affect to the USB enumeration
    because this glitch occur at USB PHY initialization which is before the USB enumeration.

    I don't know it is just one host or multiple hosts not able to enumerate.
    As far as I know, multiple USB device(include DM6446) can't enumerate to particular USB host.

    best regards,
    g.f.