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TMS320DM6467T: Output delay skew from CK falling to Addr/Cmd/Ctl required for TMS320DM6467TCUTD1

Part Number: TMS320DM6467T

I am performing DDRx batch simulation for processor "TMS320DM6467TCUTD1" interfaced with DDR2 "MT47H64M16HR-25IT:H" at the data rate of 792MT/s. While creating DDRx controller timing model some data are not able to find in datasheets.

Required data :

 1. Output delay skew from CK falling to Addr/Cmd/Ctl (max and min)

The Address and Command signals are clocked into the DRAMs on a rising clock edge.  Therefore, the controller typically outputs these signals approximately aligned with a falling clock edge. Reference images are shown below.