Other Parts Discussed in Thread: THS8200
When I run the Dm648_demo project (which reads the DIP switch to do with SD/HD i.e. s-video out / VGA out on startup), the app sys_aborts (according to the console) because
ASSERT FAILED: EVM video clock control failed in app_block_video_output.c line 685
This is an i2c command to the THS8200,
// Set the EVM video clock to 74.25 MHz (High def)
status |= APP_I2C_setHDClock();
Can it actually do 74.25 MHz? 27MHz for the PAL s-video out works OK, but in that case its set to the SAA7105. We've copied this part of the reference design in good faith that it worked, but the VGA output has never been tested.
I have a 1080i-compliant VGA display - I had been fooled by an older Samsung VGA monitor, into thinking that the VGA was there, & it was simply that the monitor couldn't sync to it, so I'm surprised that I didn't notice this message a few days ago. Is there a test point on the board where I can check the 74MHz is being generated with a scope? Perhaps its a bit temperamental! Its 27C here in my office in Scotland today (its usually 10 degrees colder!)
