Hi,
DM6446 is interfaced to FPGA in our project
We are using EDMA on DSP of processor, i have configured DM6446 EDMA to receive data on UART and McBSP, size of data on UART is 2052bytes and on McBSP it is 1628 Bytes (864 frame sync of 2bytes each).
Data on uart is configured for 2052 bytes and it can come at any time and data on mcbsp is coming every 20ms, mcbsp is clocked at 16.667MHz, 1 word of 16 bits each, so its transfer time is about 0.9ms.
When i have disabled mcbsp, uart edma is working properly and we are able to send multiple packets of 2052bytes each on it, but as soon as i have enabled mcbsp, data transfer on uart hangs after 1 packet transfer, and its uart IIR register shows interrupt pending and receive data overflow bits set
I studied the edma document of the processor and thought of using chaining, but when i am setting the intermediate chaining enable bit of OPT register, that is not showing in CER register.
Please help.
Regards.
