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DM648 GPIO0-7 pins and/or Pin Mux Register Select

Other Parts Discussed in Thread: TMS320DM647

Hello,

 The Documentation is confusing to me so I've got to ask.  I want to use the User Defined LEDs on my EVM board which are tied to GPIO2-GPIO5, but I'm not having any luck.  I believe I am setting up the GPIO module correctly, however, I'm not sure about the PinMux Select Register.  The instructions are unclear to me as to if the GPIO0-7 lines are even muxed or not (as shown in Table 3-8 in the tms320dm647 datasheet).  Also, what does Table 3-7 mean with the Unmuxed or Muxed Columns?  Is this the same as Primary and Secondary Functions of the Pins?

Thanks for any help.

--James Rasmussen

 

  • JRasmussen said:

    The Documentation is confusing to me so I've got to ask.  I want to use the User Defined LEDs on my EVM board which are tied to GPIO2-GPIO5, but I'm not having any luck.  I believe I am setting up the GPIO module correctly, however, I'm not sure about the PinMux Select Register.  The instructions are unclear to me as to if the GPIO0-7 lines are even muxed or not (as shown in Table 3-8 in the tms320dm647 datasheet).


    Table 3-8 indicates that either the PCI interface is enabled on those affected pins as denoted by the footnote #1 when UHPIEN=0, or the UHPI/GPIO are enabled when UHPIEN=1.
     

    JRasmussen said:

    Also, what does Table 3-7 mean with the Unmuxed or Muxed Columns?  Is this the same as Primary and Secondary Functions of the Pins?


    Unmuxed indicates the specified pins are going to be the indicated functionality, when enabled by the value of the register field, or will just be in a HI-Z, or 3-state mode.
    Muxed indicates that different functionality can be enabled depending on the register field.

    For instance, the SPI_UART_EN field PINMUX[13:12] controls if SPICLK is enabled, disabled or in a 3-state.  It also controls if the SPI is muxed, UART is muxed, or a combination of both is muxed out.

    SPI_UART_EN

    Pin F22 

    Pin D23 

    Pin F23

    Pin G23

    Pin F21

    00

    3-state

    3-state

    3-state

    3-state

    3-state

    01

    SPICLK

    SPICS1

    SPICS2

    SPIDI 

    SPIDO

    10

    disabled 

    UARTTX

    UARTRX

    UARTRTS

    UARTCTS

    11

    SPICLK

    UARTTX

    UARTRX

    SPIDI

    SPIDO

     


  • Thanks much! This makes it much easier to read and understand for me, as well as me being able to better decode the programming table on the pin mux.

    --James Rasmussen