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OMAP-L13x, AM1x and C674x Processors Forum
McASP on OMAP-L138
Thank you for your help.
OMAP-L138 data sheet (SLVSQ9), page154 has "McASP Timing reguirements".
The timing parameters 5 and 6 and 7 in Table 5-65 are different depending of AHCLKR/X internal or AHCLKR/X external output.
Is Data sheet correct?
As I understood - if AHCLKR/X is external output - that means it was generated internally. Is this correct?
Can you please explain in more details - what "AHCLKR/X ext output" means? What is the source for AHCLKR/X in this case?
Thank you ,
Sorry for the delay in response. The McASP expert will respond back to this in a day or two.
A few things to note
1) Looks like it should have been ACLKR/X not AHCLKR/X , and "H" is a typo (but will need for the McASP expert to confirm).
2) The external output mode is a unique mode that is never really used by any customer, and has to do with pad loopback mode that is typically used for internal timing analysis etc. So I think you can ignore that mode.
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Hi, Mukul is right.#1. It's a typo.
#2.External output basically means that you internally generate the clock, but set the pin up as an input. So you drive the clock out of the output buffer (output), but take it back into the input buffer as if it were an external source (external). FYI, here's the relevant info from the McASP user guide. As Mukul said, nobody really uses it.Finally, there is an important advantage to having separate control of pin direction (by PDIR), and thechoice of internal versus external clocking (by CLKRM/CLKXM). Depending on the specific device andusage, you might select an external clock (CLKRM = 0), while enabling the internal clock divider, and theclock pin as an output in the PDIR register (PDIR[ACLKR] = 1). In this case, the bit clock is an output(PDIR[ACLKR] = 1) and, therefore, routed to the ACLKR pin. However, because CLKRM = 0, the bit clockis then routed back to the McASP module as an "external" clock source. This may result in less skewbetween the clock inside the McASP and the clock in the external device, thus producing more balancedsetup and hold times for a particular system. As a result, this may allow a higher serial clock rate interface.Bobby T.
Thank you very much for your respond and help.
I was always thinking that #1 was a typo, thank you for clarifying that.
Is there any timing available for AHCLKX/R to ACLKX/R when AHCLKX/R (external) are used to generate ACLKX/R?
There should be some timing for that but I can't find any in DS.
Thank you for your help,
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