I have a customer using an OMAPL138 and ADS1274 and they are running into synchronization issues with the McASP bus. The data to the OMAP is either over-running or under-running. They have set up their clock source of the A/D to be 15.737 MHz to get 61kS/s on 4 input channels. The customer is using the time-division multiplexing to have all 4 data outputs on one signal.
The customer says that the 15.737 MHz SCLK line needs a 256 divider on the OMAP side, but the McASP interface's divisor goes from 0 to 32 only.
Please advise whether the McASP bus can be used for the 61kS/s output of the ADS1274. If so, how can the two parts synchronize?
Can you please show a diagram of how the two devices are connected and which device is driving which signal?
Faraz.FThey have set up their clock source of the A/D to be 15.737 MHz to get 61kS/s on 4 input channels. The customer is using the time-division multiplexing to have all 4 data outputs on one signal.
For example in this case it's not clear WHAT is the data source. Is it the OMAPL138? Is it an external clock? Does that external clock then connect to both devices? The diagram requested above would eliminate all confusion here and then hopefully we can make some suggestions.
In reply to Brad Griffis:
Left side is ADC the Right side is OMAPL138
In reply to FF:
Your image didn't come through. Instructions for posting images on e2e can be found here:
here it is,
No. Is the picture showing up when you look at the thread? How about when viewing the thread from another computer?
the left side is ADC and the right side is the OMAP
could you open the file?
Yes, I can now see the connection. However, there are many questions unanswered by the schematic:
Why is SCLK so fast? My calculations for the desired SCLK frequency are:
So in other words I believe your ACLKX should be 5.856 MHz rather than 15.737 MHz. Then you can set XMOD = 4 and everything works.
Faraz.FThe data to the OMAP is either over-running or under-running.
Are they using CLK and SCLK signals derived from different sources? If so, you're going to have clock skew issues that will cause this exact behavior. Both CLK and SCLK must be derived from the same parent clock in order to maintain synchronization.
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