Hello,I have been trying to improve ESD Immunity on OMAPL138.The usage note on silicon errata describes the following: (sprz301g: P7)
Disable the DLL REFCLK signal in the DDR EMIF PHY. This prevents the DLL used by the DDR PHY from dynamically tracking glitches on the input clock.This can be done after normal DDR initialization by setting the following bit in the DDR PHY Control Register (0xB00000E4): DRPYC1R |= 0x00002000;
Although I have refered TRM, DRPYC1R[13] bit have been reserved.
- Can I ignore reserve and set DRPYC1R[13] bit ? - If there is other way, how can I disable DLL REFCLK ?
Best regards,RY
Hi RY
RY9983 - Can I ignore reserve and set DRPYC1R[13] bit ? - If there is other way, how can I disable DLL REFCLK ?
Yes, you can ignore the reserved notification for bitfield 13 and set it to disable the DLL REFCLK as part of your DDR initialization. This bitfield was previously not relevant for regular DDR initialization/usage and therefore was marked reserved. In light of the usage note, this bitfield can now be set as recommended in the usage note.
I will submit a documentation ticket to fix the documentation and document this bitfield on a subsequent release of the TRM. Thanks for catching this.
Regards
Mukul
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Hello, Mukul.
Thank you so much for the information!I would like to try it.
Can I have an additional questions on this ?
Silicon Errata describes that DRPYC1R disable the DLL REFCLK signal.The datasheet of DDR side specifies that we need enable DLL on normal operation.
- Is DRPYC1R involved in disabling DLL?