If I am reading the code correctly, and using the PLL spreadsheet correctly, for the OMAP-L138 UBL User Boot Loader is setting PLL1 so that SYSCLK3 is 100MHz, which violates the 50MHz (and/or 75MHz) upper limit.
version 2.40:
OMAP-L138/Common/src/device.c: 236
status |= DEVICE_PLL1Init(24, 1, 0, 1, 2);
I am not sure if this will cause any actual problems but it looks suspicious.
Also, if this is indeed a problem, it may be necessary to change the PLL in stages because the initial divider settings in PLL1 may conflict with whatever is first setup in PLL0 (since this div3=2 is the default value, which is set even before the aforementioned line is called).
Hi Judson
You are correct that PLL1_SYSCLK3 if being configured for 100 MHz instead of 50 MHz etc, is violating the max pllout spec for this SYSCLK. However this will not cause any problem in your system if PLL1_SYSCLK3 is not being used in your application.
PLL1_SYSCLK3 is intended to support a unique use-case (which most customers are not using AFAIK). It is described in the system guide , Device clocking section 7.2
For PLL0 only, the EXTCLKSRC bit in PLLCTL can be configured to use PLL1_SYSCLK3 as the Bypass mode reference clock
By default this mode/option is not used.
PLL0 and PLL1 are completely independent, so PLL1 configuration will not impact the previously configured PLL0 configuration.
I will forward your email to UBL team to have this corrected in a subsequent release.
Don't forget to verify answers to your forum questions by using the green "Verify Answer" button.
Yeah, I figured it wasn't being used, I just was not sure what happens when you have a PLL clock that is out of spec. Maybe it could cause some error in hardware that would be otherwise unrelated if it was working within proper spec? No idea - hence the fear.
Mukul Bhatnagar PLL1_SYSCLK3 is intended to support a unique use-case (which most customers are not using AFAIK). It is described in the system guide , Device clocking section 7.2
In dealing with the Arago PSP code, I found these lines in arch/arm/mach-davinci/da850.c:
/* Use PLL1_SYSCLK3 for the PLL0 bypass clock */ da850_set_pll0_bypass_src(true);
However, I don't actually see it occuring (using some printk calls).