i am using a preexisting edma setup for the MCasp and i am trying to use the edma for getting data from the uart (uart2) by setting up another edma channel that triggers a different interrupt.
the first problem is that the dma does not read more than on word from the uart and the uart (in fifo mode) does not clear so that the next word can be read. although, the interrupt does occur so i can "manually" read from the uart's RBR every interrupt enabling me to get the data from the uart.
this leads to the second problem that is that when i combine the two codes (one for the MCasp and one for the uart) and want to work with both interrupts (i have set the uart's SWI to be at a higher priority) the uarts interrupts do not always work and some data is absent. i was thinking that this could be related to the "event queue" for the dma but its just a hunch. is there anything important to change in the edma's setup if i want different edma events on different channels? (there are two events for the MCasp- event0 and event1, and event 30 for the uart2).
i am working with a logicpd experimenters board with an omap-l138.
alon yaishalthough, the interrupt does occur so i can "manually" read from the uart's RBR every interrupt enabling me to get the data from the uart
Are you using BIOS PSP? If so, could you please mention which version of the PSP are you using? Looking at your post I think you are configuring UART in DMA mode only.
Have you tried executing the sample application binaries that come with the PSP? Or, have you tried just running the UART alone? If so, what is the behavior?
Let me know..
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i am not using bios psp and haven't tried executing the sample application binaries.
i have been using the uart as configured in a uart demo.
running the uart alone using an interrupt generated by the dma works fine for and interrupt every byte received, and fine after the first 3 byte if the dma is configured to generate an interrupt every 3 bytes recieved.
when i worked with the uart alone, there was a problem that the dr bit was not always indicating that there was data ready in the fifo. in my application i recieve communication to the uart in 3 byte words, sometimes after reading the first byte (under the statement (if (DR==1))) , if i would try to read from the uart again right after that, the DR byte would still be '1' and i would receive junk from the uart. i thought that this was due to the speed of the change from 1 to 0 of the data ready byte, but maybe its not and its related to the problem.
Since you are not using the BIOS driver software packages, I have moved this thread over to the OMAP-Lxx forum in hopes that you will be able to get a faster response to your question there.
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