Hello, and thanks in advance for reading my question.
I have been reading the OMAP-L138 Datasheet and Technical Reference Manual, but I have not been able to find information on how the EMA_WAIT0 signal is used in the following situation:
Consider the case where a NAND flash write occurs, which causes EMA_WAIT0 to be asserted (pulled low) by the NAND chip. While the write is taking place and EMA_WAIT0 is held low, an attempt is made to access the asynchronous memory on CS4. Does this access take place, or is EMIFA blocked until the NAND chip deasserts EMA_WAIT0? If the access does take place, how is it impacted by the fact that EMA_WAIT0 is already being asserted?
Any help would be greatly appreciated!
Bump... I'm still interested in feedback on this. I am having intermittent problems with EMIFA communication on a design that shares EMA_WAIT0 between NAND flash and an asynchronous memory (as described in my original post).
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