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TI Home » TI E2E Community » Support Forums » Digital Signal Processors (DSP) » OMAP™ Processors » OMAP-L13x, AM1x and C674x Processors Forum » Using EMA_WAIT with asynchronous memory and NAND flash
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    Using EMA_WAIT with asynchronous memory and NAND flash

    This question is not answered
    Butters
    Posted by Butters
    on Aug 29 2012 12:02 PM
    Prodigy170 points

    Hello, and thanks in advance for reading my question.

    I have been reading the OMAP-L138 Datasheet and Technical Reference Manual, but I have not been able to find information on how the EMA_WAIT0 signal is used in the following situation:

    1. NAND flash is connected to EMIFA CS3, and EMA_WAIT0 is connected to the NAND R/B pin.
    2. At the same time, an asynchronous memory is connected to EMIFA CS4, and EMA_WAIT0 is connected to it as well. The EW bit (extended wait mode enable) is set in CE4CFG.

    Consider the case where a NAND flash write occurs, which causes EMA_WAIT0 to be asserted (pulled low) by the NAND chip. While the write is taking place and EMA_WAIT0 is held low, an attempt is made to access the asynchronous memory on CS4. Does this access take place, or is EMIFA blocked until the NAND chip deasserts EMA_WAIT0? If the access does take place, how is it impacted by the fact that EMA_WAIT0 is already being asserted?

    Any help would be greatly appreciated!

    Thanks again,
    Dave

    OMAP NAND l138 EMIFA EMA_WAIT
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    • Butters
      Posted by Butters
      on Sep 26 2012 12:40 PM
      Prodigy170 points

      Bump... I'm still interested in feedback on this. I am having intermittent problems with EMIFA communication on a design that shares EMA_WAIT0 between NAND flash and an asynchronous memory (as described in my original post).

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