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  • TI Thinks Resolved

RTOS: What should be the cache-able option for shared memory for IPC

Tool/software: TI-RTOS

Hi there, I have installed IPC 3.46.00.02 and have run the ex02_messageq example on OMAPL138 and with Linux on ARM.

I don't understand the cache option added in the DSP.cfg file :

var Cache = xdc.useModule('ti.sysbios.family.c64p.Cache');
/* Set 0xc4000000 -> 0xc4ffffff to be non-cached for shared memory IPC */
Cache.MAR192_223 = 0x00000010;

I guess, the comment is wrong to start with. Here we are disabling the 0xc3000000 rather than 0xc4000000. 

Could you explain what is the idea about this cache option? should IPC memory not be cache-able ? 

Attached the full dsp.cfg file for your reference.

Thanks.2337.Dsp.cfg

  • In reply to Sahin Okur:

    Hi Sahin,

    Thanks for coming back.

    I have changed the createHeap settings to false and creating heap using the HeapMemMP but the design fails to compile.

    Error: HeapMemMP does not support static instances.

    Can I do the following:

    /* Shared Memory base address and length */
    var SHAREDMEM = 0xc0000000;//0x80001400;
    var SHAREDMEMSIZE = 0x00020000;

    /*
    * Need to define the shared region. The IPC modules use this
    * to make portable pointers. All processors need to add this
    * call with their base address of the shared memory region.
    * If the processor cannot access the memory, do not add it.
    */
    var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
    SharedRegion.setEntryMeta(0,
    { base: SHAREDMEM,
    len: SHAREDMEMSIZE,
    ownerProcId: 0,
    isValid: true,
    createHeap: false,//true,
    cacheEnable: true,
    name: "SharedMem",
    });

    /* create a heap for MessageQ messages */
    var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
    var params = new HeapBuf.Params;
    params.align = 8;
    params.blockSize = 512;
    params.numBlocks = 256;
    //params.sectionName = "testHeap";
    var msgHeap = HeapBuf.create(params);

    //Program.sectMap["testHeap"] = "SharedMem"; //"DDR";

    var MessageQ = xdc.useModule('ti.sdo.ipc.MessageQ');
    MessageQ.registerHeapMeta(msgHeap, 0);

    But not sure how will msgHeap would be allocated from SharedMem.

    Could you please, explain, Thanks.

  • In reply to Sahin Okur:

    Hi Sahin, I tried the folowing as you suggested.
    But still getting error even to compile the design.

    Added in C code:
    HeapBufMP_Params heapParams;
    HeapBufMP_Handle heapHandle;
    HeapBufMP_Params_init(&heapParams);
    heapParams.regionId = 1;
    heapHandle = HeapBufMP_create(&heapParams, &eb);

    MessageQ_registerHeap(heapHandle, 1);


    One more thing, I am not 100% sure is would I be able to use the sharedRam for IPC between DSP and ARM/Linux core?
  • In reply to Mitesh Hiran:

    This is the error, I get from CCS:

    undefined first referenced
    symbol in file
    --------- ----------------
    ti_sdo_ipc_heaps_HeapBufMP_Params__init__S ./main.obj
    ti_sdo_ipc_heaps_HeapBufMP_create ./main.obj

    error #10234-D: unresolved symbols remain
  • In reply to Sahin Okur:

    Hi Sahin,
    Right, so as per you previous reply,
    I have left the SharedRegion configuration, createHeap to "true" and removed the extra HeapMemMP instance from the cfg file.

    I have then added
    MessageQ_registerHeap(SharedRegion_getHeap(1), 1);
    in C code. I believe, we need to add this so that messageQ are allocated from this SharedRegion . Does this makes sense?

    ROV View of SharedRegion: id 1:
    ,1,0x80001400,0x800033ff,0x2000,0,false,true,8,0,0x0,SharedRAM

    Got the following Error in CCS:
    3 Resource entries at 0xc3110000
    [t=0x0a2aac5f] ti.sdo.ipc.MessageQ: ERROR: line 191: assertion failure: A_heapIdInvalid: heapId is invalid
    ti.sdo.ipc.MessageQ: line 191: assertion failure: A_heapIdInvalid: heapId is invalid
    xdc.runtime.Error.raise: terminating execution


    In the C code: I have used the following:
    MessageQ_registerHeap(SharedRegion_getHeap(1), 1);

    And the CFG:
    /* Shared Memory base address and length */
    var SHAREDMEM = 0x80001400;
    var SHAREDMEMSIZE = 0x00002000;

    /*
    * Need to define the shared region. The IPC modules use this
    * to make portable pointers. All processors need to add this
    * call with their base address of the shared memory region.
    * If the processor cannot access the memory, do not add it.
    */
    var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
    SharedRegion.setEntryMeta(1,
    { base: SHAREDMEM,
    len: SHAREDMEMSIZE,
    ownerProcId: 0,
    isValid: true,
    createHeap: true,
    cacheEnable: false,
    cacheLineSize: 0,
    name: "SharedRAM",
    });


    Also try the following in C code:
    MessageQ_registerHeap(SharedRegion_getHeap(SharedRegion_getIdByName("SharedRAM")), 1);

    no luck.
  • In reply to Mitesh Hiran:

    Hi Mitesh,

    I think we are getting closer...

    In the code, is messageQ_registerHeap being called before MessageQ_alloc? If not, that could be a potential cause of the "heapId is invalid" error.

    Also, I believe you need to create a SharedRegion 0 since it is used by IPC_start() to create resource management tables for internal use by other IPC modules (refer to processors.wiki.ti.com/.../SharedRegion_Module). It looks like you are just creating SharedRegion 1.

    Hope this helps. Keep us posted!

    Regards,
    Sahin

    Sahin Okur
    Applications Engineer

  • In reply to Sahin Okur:

    Hi Sahin,
    I have called messageQ_registerHeap in C code before the MessageQ_alloc.
    About having SR0 for IPC, can I do the following:

    /* Shared Memory base address and length */
    var SHAREDMEM = 0xc3200000;//0x80001400;
    var SHAREDMEMSIZE = 0x00020000;

    /*
    * Need to define the shared region. The IPC modules use this
    * to make portable pointers. All processors need to add this
    * call with their base address of the shared memory region.
    * If the processor cannot access the memory, do not add it.
    */
    /*var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
    SharedRegion.setEntryMeta(0,
    { base: SHAREDMEM,
    len: SHAREDMEMSIZE,
    ownerProcId: 0,
    isValid: true,
    createHeap: true,
    cacheEnable: false,
    cacheLineSize: 0,
    name: "SharedRAM0",
    });*/

    /* Shared Memory base address and length */
    //var SHAREDMEM1 = 0xc200000;//0x80001400;
    //var SHAREDMEMSIZE1 = 0x00020000;

    /*
    * Need to define the shared region. The IPC modules use this
    * to make portable pointers. All processors need to add this
    * call with their base address of the shared memory region.
    * If the processor cannot access the memory, do not add it.
    */
    /*var SharedRegion = xdc.useModule('ti.sdo.ipc.SharedRegion');
    SharedRegion.setEntryMeta(1,
    { base: SHAREDMEM1,
    len: SHAREDMEMSIZE1,
    ownerProcId: 0,
    isValid: true,
    createHeap: true,
    cacheEnable: false,
    cacheLineSize: 0,
    name: "SharedRAM1",
    });*/

    var MessageQ = xdc.useModule('ti.sdo.ipc.MessageQ');
    //MessageQ.registerHeapMeta(IPCHeap, 0);

    /* Setup MessageQ transport */
    var VirtioSetup = xdc.useModule('ti.ipc.transports.TransportRpmsgSetup');
    MessageQ.SetupTransportProxy = VirtioSetup;

    /* Setup NameServer remote proxy */
    var NameServer = xdc.useModule("ti.sdo.utils.NameServer");
    var NsRemote = xdc.useModule("ti.ipc.namesrv.NameServerRemoteRpmsg");
    NameServer.SetupProxy = NsRemote;

    /* Enable Memory Translation module that operates on the BIOS Resource Table */
    var Resource = xdc.useModule('ti.ipc.remoteproc.Resource');
    Resource.loadSegment = "DDR";

    /* Use SysMin because trace buffer address is required for Linux/QNX
    * trace debug driver, plus provides better performance.
    */
    var System = xdc.useModule('xdc.runtime.System');
    var SysMin = xdc.useModule('xdc.runtime.SysMin');
    System.SupportProxy = SysMin;
    SysMin.bufSize = 0x8000;

    Program.sectMap[".tracebuf"] = "DDR";
    Program.sectMap[".errorbuf"] = "DDR";

    var Cache = xdc.useModule('ti.sysbios.family.c64p.Cache');
    /* Set 0xc4000000 -> 0xc4ffffff to be non-cached for shared memory IPC */
    Cache.MAR192_223 = 0x00000008;

    /* Override the default resource table with my own */
    var Resource = xdc.useModule('ti.ipc.remoteproc.Resource');
    Resource.customTable = true;


    And In C Code:
    MessageQ_registerHeap(SharedRegion_getHeap(SharedRegion_getIdByName("SharedRAM1")), 1);
    Not sure if the heapID should be 0 or 1.

    Where will the messageQ_alloc will allocate memory from?? would it be 0xc20000000?
    And would I be able to use this to communicate with remoteproc in Linux??

    Thanks.
  • In reply to Mitesh Hiran:

    Hi Mitesh,

    The configuration looks ok. The heapID depends on which heap you want to allocate messageQ from (refer to downloads.ti.com/.../_message_q_8h.html
    downloads.ti.com/.../_shared_region_8h.html )

    messageQ_alloc will allocate memory from the heap specified with the heapID.

    Did you run into any errors when running this configuration? If so, what were they?

    Also, did you already refer to the src and cfg files in ex02_messageQ? I think that example does what you are trying to do here.

    Regards,
    Sahin

    Sahin Okur
    Applications Engineer

  • In reply to Sahin Okur:

    Happy New Year Sahin, thanks for your reply.

    I have gone through the C code of the Messageq_ex02 example. However, when I just make one change

    1) 

    var Cache = xdc.useModule('ti.sysbios.family.c64p.Cache');
    /* Set 0xc4000000 -> 0xc4ffffff to be non-cached for shared memory IPC */
    Cache.MAR192_223 = 0x00000010;

    to 

    var Cache = xdc.useModule('ti.sysbios.family.c64p.Cache');
    /* Set 0xc4000000 -> 0xc4ffffff to be non-cached for shared memory IPC */
    Cache.MAR192_223 = 0x00000008;

    And the example stops working... 

    Could you help me to get this working, please.

  • In reply to Mitesh Hiran:

    Hello Mitesh,

    Happy New Year!

    The line

    Cache.MAR192_223 = 0x00000008;

    sets 0xc3000000 -> 0xc3ffffff to be cached. I believe the Vring buffers are placed in this region by default. Vring buffer regions need to be marked as uncached so make sure that you are placing them outside the cached region.

    Regards,
    Sahin

    Sahin Okur
    Applications Engineer

  • In reply to Sahin Okur:

    Hi Sahin, thanks for your reply.

    I did try that in the past but I was not able to boot Linux.

    Here are the changes I had done:

     * Changed Resource table address for VRINGS to 0xc2000000

     * Changed DSP app to run from 0xc3000000

     * Made 0xc3000000 Cache-able 

     * In DTS file changed CMA region to be 0xc2000000 of lenth 0x02000000

    But the linux was not able to boot!/...

    Would you be able to create a new ex02 example with cache enabled for the DSP app and VRING in non-cache region for me, please?

    Thanks.

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