Setting up samplerate on AD-DA converters of the DSKDA830

Hello,

I'm not sure what the sample code looks like.  But I can tell you that our usual flow is as follows:

-AK4588 provides BCLK and LRCK to a receiving McASP, for SPDIF reception.

-AK4588 provides an MCLK to the transmitting McASP

-McASP uses that MCLK to generate BCLK and LRCK and feed them to the DAC section of the AK4588.

You mention that the sample rate is 41.7 kHz...which clock are you looking at?  The LRCK generated by the McASP?  Or the one sent to the receiving McASP by the AK4588?  What does your I/O look like, is it analog in/analog out?  Or SPDIF in?  If SPDIF, have you set the selector switch properly (it picks between coax and optical input)?

Usually the output MCLK is dependent upon whatever the SPDIF input to the AK4588 is.  If you have no SPDIF input, I'm not sure exactly what MCLK the AK4588 will spit out, as the 4588's PLL has nothing to lock to.

Search the AK4588 manual for "CM0/CM1."  There should be a table; I believe you want mode 2, where if SPDIF is locked, the MCLK source is the PLL, but if there is no lock, the source is the xtal.  The xtal is 24.576 MHz, which will divide down cleanly to 48 kHz.  This is helpful, as typically when you use SPDIF input, having the MCLK based on whatever is coming in (i.e. PLL) makes sense, but if you're doing ADC input, you may or may not have SPDIF clock to use as a reference.

Tip: In our code, whenever we choose ADC input, we force the SPDIF receiver to unlock; we do this by picking one of the unused SPDIF inputs (see the table "recovery data select" in the 4588 manual).  Since there's no input, the device goes into UNLOCK, and you immediately get the crystal's 24.576 MHz as your MCLK.  You could achieve the same effect by yanking the SPDIF cable, but this is easier, especially if you're switching back and forth between SPDIF and analog inputs.

Hope this helps.

Bobby T.

Hi,

yes, that really helped, thank you. In the original version of the software, 0x4b was written to the register "CLK & Power Down Control". By setting CM1 = CM0 = 1 (0x7b in that register), I now see a sampling frequency of 96 kHz. That is not what I intended but it is much better than before.

To the details: I use only analog I/O. I measured the clock rate by measuring the number of cycles between frames of audio samples and I verified this by outputting a 1000 Hz signal and comparing that to a verification audio signal of 1000 Hz. That gave me the 41.7 kHz. I do not involve any logic analyzer, so I can not see any clocks directly.

So it seems that now I use the 24.576 MHz clock (X'tal).

Do you also see a way to get 48 kHz instead of 96 kHz? What I do for configuration of audio I/O is to write the following values to the ak4588:

Control 1: 0x0C -> 24-bit I2S mode
Control 2: 0x80 ->  Master clock is 512 x fs, normal speed mode
Att speed & Power Down Control: 0x01 ->Take AK4588 out of reset
CLK & Power Down Control: 0x7B -> Normal Operation, MCK0 = 512 x fs, Clock Source: X'Tal

And here is how I setup McAsp1:

RMASK: 0xffffffff -> No padding used
RFMT: 0x000180f0 -> MSB 32bit, 1-delay, no pad, DATABus
AFSRCTL: 0x00000112 -> 2TDM, Rising, INTERNAL FS, word
ACLKRCTL: 0x000000A3 -> Rising INTERNAL CLK, div-by-4
AHCLKRCTL: 0x00000000 -> EXTERNAL CLK
RTDM: 0x00000003; -> Slots 0,1
RCLKCHK: 0x00FF0008 -> 255-MAX 0-MIN, div-by-256

The transmit side is set accordingly:

XMASK: 0xffffffff -> No padding used
XFMT: 0x000180f0 -> MSB 32bit, 1-delay, no pad, DATABus
AFSXCTL: 0x00000112 -> 2TDM, Rising edge INTERNAL FS, word
ACLKXCTL: 0x000000E3 -> ASYNC, Rising INTERNAL CLK, div-by-4
AHCLKXCTL: 0x00000000 -> EXTERNAL CLK
XTDM: 0x00000003 -> Slots 0,1
XCLKCHK: 0x00FF0008

These values are taken - except for the correction made following your hint in the first email - from the Spectrum Digital test code.

If XTal is 24.576 MHz and Control 2 is 0x80, the setup is not supposed to output 96 kHz at all, is it?

Thank you and best regards,

HT

Hi,

OK, first of all--I really suggest that you borrow an oscilloscope.  You may be able to figure out what your sampling rate is based on whatever you did, but unless you are able to measure each clock at the appropriate node, you don't know for sure what's going on.  You'll probably run into more issues where a scope will become necessary.

That said--I see a couple of issues.  First--if you're doing I2S (which I assume that you are, based on the 2-ch TDM and the 1-bit delay), you need the FALLING edge to indicate the beginning of a frame.  You have it set to RISING.  And don't forget to specify MSB first.

You also have the polarity bit for ACLKX and ACLKR set to RISING.  Remember that if a transmitter clocks out data on the falling edge of the bit clock, then the receiver must clock it in on the rising edge, and vice versa.  If this were some generic case, then I'd say to go and verify the expected polarity of whatever device you're writing to/receiving data from.  But since I know it's the 4588, I can tell you that in our app, for ADC in/DAC out we set the Tx bit clock polarity to falling edge, and the Rx bit clock polarity to rising edge.

Your 96 kHz sample rate is due to your setting the ACLKX/ACLKRDIV value incorrectly.  You are receiving a 24.576 MHz MCLK, and dividing it by 4; this gets you a bit clock of 6.144 MHz.  Divide that by 64 (two 32-bit slots per frame gives you 64 bits per frame) and you end up with 96 kHz.  You want to set the ACLKX/ACLKRDIV to divide by 8 instead.  That'll get you to 48 kHz.

I suggest that you set CM0/CM1 to mode 2.  You'll still get the behavior you're getting now (since you don't have S/PDIF input, your state is always UNLOCK), but if you ever decide to add S/PDIF functionality, it'll still work.  If later you add S/PDIF and forget to change the clock mode, you'll have issues.

Good luck.

Bobby T.

Hi,

thank you once more. Again, your mail really helped me very much!

It may be that the setup of the ak4588 and the McAsp1 seems a little odd to you since the hardware is a little odd: The ak4588 is only used for DAC, and 4 PCM1802 are used for ADC to allow for 8 input and output channels.

I modified the divisor to 8 and also 12 and now I can operate the device at 48 and 32 kHz which is perfect! One of the things that I did not read properly was that for a divisor of N, I need to setup a value of (N-1) in the register ACLKXCT!

Once again, thank you very much!

Best regards,

HT

Hi,

even though this thread was solved before, I have an additional issue regarding the ak4588, maybe you also know how to solve it:

Thanks to the previous answers, I have configured the device to operate at 32 and 48 kHz samplerate now. If doing so, I need to setup the de-emphasis filter. For this reason I write to register "Format & De-em Control" (in the original documentation):

For 32 kHz -> 0x66

For 48 kHz -> 0x64

To set these values, however, has no impact, still I have strong aliasing problems with 32 kHz operation mode. The only possible reason in my opinion is that the PEM bit is somehow set to 0. Does anyone have any idea?

Best regards,

HT

Hi, sorry, can't really help on this one.  I know the basics of the AK4588 set up but this one is beyond me.  I'd suggest contacting AKM for support, they have always been responsive when I had questions.

Bobby T.

Well, bad luck, thank you anyway for responding!

Best regards

HT