Hi,
I am in the process of developing a program that has audio pass through using ping pong buffers (I took the audio_edma_c6747.prj which uses semaphores as example- http://software-dl.ti.com/dsps/dsps_public_sw/c6000/web/c6747_audio_edma_app/latest/index_FDS.html). I want to convert this into 8KHz sampling rate (not 48KHz sampling rate). For this, I made the codec to be master (I turned on the PLL) and McASP as slave (in the example code it was the other way- that is, codec was slave and McASP was master and McASP clocked the codec). Also I changed the 24.576MHz crystal near the codec (in the EVM board)to 2.048MHz crystal. I did the following changes in the registers. But, then, the program flow doesnt return after the SEM_pend(&sem, SYS_FOREVER); - in one of the other posts in ti forum, I read that if sem_pend doesnot return, then it means the clock configurations are not correct (pls see: http://e2e.ti.com/support/embedded/bios/f/355/t/65460.aspx). The following are my configurations- are there any flaws in the clock configuration?
// Configure AIC3106 registers EVMC6747_AIC3106_rset( 2, 0xAA ); EVMC6747_AIC3106_rset( 3, 0xA1); // 5 PLL A EVMC6747_AIC3106_rset( 4, 0xC0 ); // 4 PLL B EVMC6747_AIC3106_rset( 5, 0x0 ); // 5 PLL C EVMC6747_AIC3106_rset( 6, 0x0 ); // 6 PLL D EVMC6747_AIC3106_rset( 7, 0x0A ); // 7 Codec Datapath Setup <- [FS=48 kHz][LeftDAC=LEFT][RightDAC=RIGHT] EVMC6747_AIC3106_rset( 8, 0x00 ); // 8 Audio Interface Control A <- [BCLK=Slave][MCLK=Slave] EVMC6747_AIC3106_rset( 9, 0x00 ); // 9 Audio Interface Control B <- [I2S mode][16 bit] EVMC6747_AIC3106_rset( 10, 0x00); // 10 Audio Interface Control C <- [Data offset=0] EVMC6747_AIC3106_rset( 15, 0 ); // 15 Left ADC PGA Gain <- [Mute=OFF] EVMC6747_AIC3106_rset( 16, 0 ); // 16 Right ADC PGA Gain <- [Mute=OFF] EVMC6747_AIC3106_rset( 19, 0x04 ); // 19 LINE1L to Left ADC <- [SingleEnd][Gain=0dB][Power=ON][SoftStep=OncePerFS] EVMC6747_AIC3106_rset( 22, 0x04 ); // 22 LINE1R to Right ADC <- [SingleEnd][Gain=0dB][Power=ON][SoftStep=OncePerFS] EVMC6747_AIC3106_rset( 27, 0 ); // 27 Left AGC B <- [OFF] EVMC6747_AIC3106_rset( 30, 0 ); // 30 Right AGC B <- [OFF] EVMC6747_AIC3106_rset( 37, 0xE0 ); // 37 DAC Power & Output Dvr <- [LeftDAC=ON][RightDAC=ON][HPLCOM=SingleEnd] EVMC6747_AIC3106_rset( 38, 0x10 ); // 38 High Power Output Dvr <- [HPRCOM=SingleEnd][ShortCircuit=OFF] EVMC6747_AIC3106_rset( 43, 0 ); // 43 Left DAC Digital Volume <- [Mute=OFF][Gain=0dB] EVMC6747_AIC3106_rset( 44, 0 ); // 44 Right DAC Digital Volume <- [Mute=OFF][Gain=0dB] EVMC6747_AIC3106_rset( 47, 0x80 ); // 47 DAC_L1 to HPLOUT Volume <- [Routed] EVMC6747_AIC3106_rset( 51, 0x09 ); // 51 HPLOUT Output <- [Mute=OFF][Power=ON] EVMC6747_AIC3106_rset( 58, 0 ); // 58 HPLCOM Output <- [] EVMC6747_AIC3106_rset( 64, 0x80 ); // 64 DAC_R1 to HPROUT Volume <- [Routed] EVMC6747_AIC3106_rset( 65, 0x09 ); // 65 HPROUT Output <- [Mute=OFF][Power=ON] EVMC6747_AIC3106_rset( 72, 0 ); // 72 HPRCOM Output <- [] EVMC6747_AIC3106_rset( 82, 0x80 ); // 82 DAC_L1 to LEFT_LOP/M Volume <- [Routed] EVMC6747_AIC3106_rset( 86, 0x09 ); // 83 LINE2R to LEFT_LOP/M Volume <- [] EVMC6747_AIC3106_rset( 92, 0x80 ); // 92 DAC_R1 to RIGHT_LOP/M Volume <- [Routed] EVMC6747_AIC3106_rset( 93, 0x09 ); // 93 RIGHT_LOP/M Output <- [Mute=OFF][Power=ON] EVMC6747_AIC3106_rset( 101, 0x00 ); // 101 GPIO Control Register B EVMC6747_AIC3106_rset( 102, 0 ); // 102 Clock Generation Control <- [PLLCLK_IN and CLKDIV_IN use MCLK] // Initialize MCASP1 mcasp = &MCASP_MODULE_1; /* ---------------------------------------------------------------- * * * * McASP1 is in MASTER mode. * * BCLK & WCLK come from McASP1 * * DIN is used by write16/write32 * * DOUT is usec by read16/read32 * * * * ---------------------------------------------------------------- */ mcasp->regs->GBLCTL = 0; // Reset mcasp->regs->RGBLCTL = 0; // Reset RX mcasp->regs->XGBLCTL = 0; // Reset TX mcasp->regs->PWRDEMU = 1; // Free-running // RX mcasp->regs->RMASK = 0xffffffff; // No padding used mcasp->regs->RFMT = 0x00018078; // MSB 16bit, 1-delay, no pad, CFGBus mcasp->regs->AFSRCTL = 0x00000110; // 2TDM, 1bit Rising, INTERNAL FS, word mcasp->regs->ACLKRCTL = 0x00000087; // Rising INTERNAL CLK,(from tx side) mcasp->regs->AHCLKRCTL = 0x00000000; // INT CLK (from tx side) mcasp->regs->RTDM = 0x00000003; // Slots 0,1 mcasp->regs->RINTCTL = 0x00000000; // Not used mcasp->regs->RCLKCHK = 0x00FF0001; // 255-MAX 0-MIN, div-by-256 // TX mcasp->regs->XMASK = 0xffffffff; // No padding used mcasp->regs->XFMT = 0x00018078; // MSB 16bit, 1-delay, no pad, CFGBus mcasp->regs->AFSXCTL = 0x00000110; // 2TDM, 1bit Rising edge INTERNAL FS, word mcasp->regs->ACLKXCTL = 0x00000087; // ASYNC, Rising INTERNAL CLK, div-by-16 mcasp->regs->AHCLKXCTL = 0x00000000; // EXT CLK mcasp->regs->XTDM = 0x00000003; // Slots 0,1 mcasp->regs->XINTCTL = 0x00000000; // Not used mcasp->regs->XCLKCHK = 0x00FF0001; // 255-MAX 0-MIN, div-by-256 mcasp->regs->SRCTL5 = 0x000D; // MCASP1.AXR1[5] --> DIN mcasp->regs->SRCTL0 = 0x000E; // MCASP1.AXR1[0] <-- DOUT mcasp->regs->PFUNC = 0; // All MCASPs mcasp->regs->PDIR = 0x14000020; // All inputs except AXR0[5], ACLKX1, AFSX1
(I tried PDIR = 0xA0000020 and also 0x20 - both had no effects)
mcasp->regs->DITCTL = 0x00000000; // Not used mcasp->regs->DLBCTL = 0x00000000; // Not used mcasp->regs->AMUTE = 0x00000000; // Not used // Starting sections of the McASP mcasp->regs->XGBLCTL |= GBLCTL_XHCLKRST_ON; // HS Clk while ( ( mcasp->regs->XGBLCTL & GBLCTL_XHCLKRST_ON ) != GBLCTL_XHCLKRST_ON ); mcasp->regs->RGBLCTL |= GBLCTL_RHCLKRST_ON; // HS Clk while ( ( mcasp->regs->RGBLCTL & GBLCTL_RHCLKRST_ON ) != GBLCTL_RHCLKRST_ON ); mcasp->regs->XGBLCTL |= GBLCTL_XCLKRST_ON; // Clk while ( ( mcasp->regs->XGBLCTL & GBLCTL_XCLKRST_ON ) != GBLCTL_XCLKRST_ON ); mcasp->regs->RGBLCTL |= GBLCTL_RCLKRST_ON; // Clk while ( ( mcasp->regs->RGBLCTL & GBLCTL_RCLKRST_ON ) != GBLCTL_RCLKRST_ON ); mcasp->regs->XSTAT = 0x0000ffff; // Clear all mcasp->regs->RSTAT = 0x0000ffff; // Clear all mcasp->regs->XGBLCTL |= GBLCTL_XSRCLR_ON; // Serialize while ( ( mcasp->regs->XGBLCTL & GBLCTL_XSRCLR_ON ) != GBLCTL_XSRCLR_ON ); mcasp->regs->RGBLCTL |= GBLCTL_RSRCLR_ON; // Serialize while ( ( mcasp->regs->RGBLCTL & GBLCTL_RSRCLR_ON ) != GBLCTL_RSRCLR_ON ); // Write a 0, so that no underrun occurs after releasing the state machine mcasp->regs->XBUF5 = 0; mcasp->regs->RBUF0 = 0; mcasp->regs->XGBLCTL |= GBLCTL_XSMRST_ON; // State Machine while ( ( mcasp->regs->XGBLCTL & GBLCTL_XSMRST_ON ) != GBLCTL_XSMRST_ON ); mcasp->regs->RGBLCTL |= GBLCTL_RSMRST_ON; // State Machine while ( ( mcasp->regs->RGBLCTL & GBLCTL_RSMRST_ON ) != GBLCTL_RSMRST_ON ); mcasp->regs->XGBLCTL |= GBLCTL_XFRST_ON; // Frame Sync while ( ( mcasp->regs->XGBLCTL & GBLCTL_XFRST_ON ) != GBLCTL_XFRST_ON ); mcasp->regs->RGBLCTL |= GBLCTL_RFRST_ON; // Frame Sync while ( ( mcasp->regs->RGBLCTL & GBLCTL_RFRST_ON ) != GBLCTL_RFRST_ON );}//------------------------------------------------------------------------------// End of File mcasp.c//------------------------------------------------------------------------------
Can you please send an example code that uses SEM_pend(&sem, SYS_FOREVER); and external clock for McASP (that is McASP as slave and Codec as master). Even if you provide an example code with just the McASP as slave, that would be much appreciated.
Thanks for your help.
Tharangini,
The other forum post you linked to refers to a situation where SEM_pend had a finite timeout specified. You used SYS_FOREVER for your timeout value, which means that the operation will never actually timeout. For this reason, I don't believe that this is a clock issue. Instead, I think the issue is that SEM_post is never being called. I'm guessing that SEM_post is called in your ISR, so that probably means that you are never reaching the ISR in the first place. You may want to place a breakpoint inside the ISR to verify whether or not you reach it. If not, something may have gone wrong in your peripheral setup.
Hope this helps.
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