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OMAP-L138 uPP timing question
I have a question regarding the timing of the uPP clock, start, enable and data signals. The uPP User's Guide (Literature Number SPRUGJ5B) makes a vague statement in section 2.5.6 that I would like help clarifying. See the snippet below
"The uPP transmitter drives the CLOCK signal to align all other uPP signals. By default, other signals align on the rising edge of CLOCK, but its polarity is controlled by the CLKINVx bit in UPICR. The active edge(s) of CLOCK should always slightly precede transitions of other uPP signals. "
I'm confused by the last sentence. I have a FPGA transmitting data to the OMAPL138 via the uPP. How should I interpret "The active edge of CLOCK should always slightly preceded transitions of other uPP signals". How much time satisfies a "slight" amount? Is there another document I'm missing with electrical timing specifications?
Thanks for your time,
This post hasn't been answered, this is why I hope this reply will make it live again.
I also need the timing specifications of the UPP interface to be able to perform my FPGA timing analysis.
I can't find in any of the OMAP documentations the timing specifications of the UPP signals.
At least, I require, for an :
* UPP transmit interface: the Tclock_to_out of the START/ENABLE/DATA signals and the Tsetup/Thold for the WAIT signal relative to the UPP_CLK edges (ideally at OMAP pad level)
* UPP receive interface: the Tsetup/Thold of START/ENABLE/DATA signals relative to the UPP_CLK edges (ideally at OMAP pad level)
Thanks in advance for a reply.
- The Technical reference manual (here for OMAP-L13x it is SPRUH77a) usually does not include any timings. It rather details the functionalities.For timings you need to look at the section 5.26 of the datasheet - SPRS586D:http://www.ti.com/product/omap-l138Also make sure to look at the silicon errata SPRZ301H to look at the selection exceptions.
There are as well some UPP information on the twiki: http://processors.wiki.ti.com/index.php/Introduction_to_uPP
It seems that criticallink did use the UPP to interface to an FPGA on their mitiDSP board. You might find more info from their page:http://www.mitydsp.com/products-services/base-boards/mitydsp-l138f-dev-kit/http://support.criticallink.com/redmine/projects/arm9-platforms/wiki
- Also some more general wiki articles that can helps to understand the OMAP-L138 architecture:http://processors.wiki.ti.com/index.php/Category:OMAPL1OMAP-L1x/C674x/AM1x LCD Controller (LCDC) Throughput and Optimization TechniquesOMAP-L1x/C674x/AM1x Multichannel Audio Serial Port (McASP) Throughput and Optimization TechniquesOMAP-L1x/C674x/AM1x SOC Architecture and Throughput OverviewOMAP-L1x/C674x/AM1x SoC Architectural OverviewOMAP-L1x/C674x/AM1x SoC ConstraintsOMAP-L1x/C674x/AM1x SoC Level Optimizations
Hope it helps.Anthony
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