What is Maximum Throughput for EDMA , EMIF and UPP in OMAP L138

Most the throughput and driver performances have been archived here:

http://processors.wiki.ti.com/index.php/OMAP-L138_Software_Design_Guide#Peripheral_Throughput_optimization

http://processors.wiki.ti.com/index.php/OMAP-L138_Software_Design_Guide#Software_Performance

Let us know if this helps or if you have any further questions.

Regards,

Rahul

Dear Rahul , Thanks for the link they provided me some path to check the throughput. 

Can you please help me for the following and please correct me if my understanding is going in wrong direction :-

A) EDMA Throughput

     Going by the link , what i understood is that the MAXIMUM throughput achievable is somewhere around  532Mbytes/sec. 

     This throughput is for 4k buffer , A sync mode , Self chained & self linked setting

     a.1 ) Is the source & destination both on board memory 

                          or 

              Either source or Destination is on board memory & destination is external interface like FPGA mapped via emif

    b.1) With the test i performed i am getting around 82 MBYTES /sec for on board [i.e source & destination both are on board memory ]

             And around 17 Mbytes with OMAP to FPGA with EMIF conneected in between . 

             [ My configuration is 1k Buffer ,A sync mode , and the PARAM is self linked ]

             I am not configuring any value for RDRATE register[Default value "0"] and Defalut Burst Size [16 bytes by default]

Can you please suggest some mechanism to increase the throughput .

B) EMIF interface 

     Presently i have configured EMIF interface to setup/strobe/hold as 2/4/2 . 

     And clock at 91.2 Mhz . 

    What should be approx THROUGHPUt i should expect from the interface.I am driving EMIF with EDMA

    [My understanding i will get  [   91/value] MBytes where value is [2+4+2]   ]

Please do correct me wherever my undersatning is wrong.

I am working with these interface for the first time .

Thank You,

Ashish  

Dear Rahul  , 

Can you please help me to resolve this issue . 

Thank You,

Ashish Mishra 

Hi Ashish

Your understanding on EMIF throughput is correct, with a 91.2 MHz clock  , 2/4/2 setup hold strobe etc, the max theoretical throughput you can get is (EMIFA Clock/(Setup+Strobe+Hold)) * bus width (bytes) per second.

The actual throughput should be slightly less, based on overheads through chip topology, things like un optimized EDMA transfers (due to geometry constrains of your transfer etc).

On EDMA the max throughput you quoted is roughly 80-90% throughput possible from external memory (mDDR) or internal RAMs ... i.e. e.g. for DDR2 it would be 150 MHz x 2 (double data rate) x 2 (16 bits) = 600 Mbytes/sec. Typically the best throughput you can get from EDMA would depend on the max throughput of the slower end point (source or dest) , so if you are doing L2 to EMIFA transfers, the best throughput possible will be max theoretical throughput achievable by EMIFA (and not L2) etc.

Hope this helps

Regards

Mukul

Dear Mukul , 

Thanks for the input. 

Referring to link http://processors.wiki.ti.com/index.php/OMAP-L1x/C674x/AM1x_SoC_Constraints

• Illustrated calculations assume a Setup/Strobe/Hold value of 1 cycle 
• Assumes a 16 bit async interface

Dear Mukul , 

Can you please guide me for the same 

Hi All, 

After some work the following are the out come we have arrived to :-

a) EMIF with 92.2 Mhz

     Theoretical :- 21MBytes  [ with 1 clk for strobe ,1 clk for hold , 1 for start ]

     Practical      :- 17 MBytes [ with 2 clk for strobe ,4 clk for hold , 2 for start ]

B) EDMA  with 1k Buffer :- Got 82MBytes /sec

c) UPP :- Just Started on the same will keep updated 

for DDR2 it would be 150 MHz x 2 (double data rate) x 2 (16 bits) = 600 Mbytes/sec

Interesting. We have the DDR set up to run at 150MHz, and ran some benchmarks before and after, and indeed saw a 10% improvement over the 133MHz numbers. The best we've seen is about 75 MB/s reading from DDR RAM to CPU. Can you explain why reading RAM is only at 15% of what one could expect?

 Hi Mike , 

1. The said throughput you are getting is from ARM or DSP. I am evaluating with ARM+LINUX

2. Also i have configured the EDMA Param to self LINK. 

    Probably you can configure to SELF LINK mode. 

Ashish .K Mishra 

[Banglore / India ]

I'm only using the ARM side under Linux. Tried with some own code, and with the "lmbench" publicly available code, which agrees with my findings. The CPU runs at 456MHZ, the DDR at 150MHz.

But i'm not using any DMA, so I may be hijacking your thread here... But I'd expect that the CPU to RAM interface should be (at least) equally fast as the DMA.

Dear Mike ,

It's always good to have the THROUGHPUT analysis of one more entity to give clear picture of device .

Can you please share the TEST SET up , as i haven't evaluated for DDR2 ?   

Neither have i ever used "lmbench"  !!!!!!

Ashish K Mishra ,

[Banglore / India ]

We use a LogicPD SOM module, which has mDDR if I'm not mistaken. I can share the benchmark results. "lmbench" is open source and can easily be cross-compiled for the ARM. It copies data around in memory and measures throughput.

Horizontal is the speed in MHz of the CPU. This is the result using 16MB RAM.

I did some changes to the DDR timing settings, and repeated the tests with the CPU running at 456 MHz.

As you can see, increasing the frequency and lowering timings had a positive effect. Even with the fastest settings as displayed above, the system is stable, an memtest can be run for hours without errors.

Hi Mike,

I just start to work on emif to fpga on Linux system. From your post, I think you already go ahead on me on this topic.

I come to ask if you can help on how to map the emif memory on Linux system. What documents you have referenced while working this topic. What files I should look into? If you had posted steps how to this mapping that will be great appreciated.

Best Regards,

Joe

Hi Joe,

Always better to create new thread for your question or problem since old threads may get less attention than new one.

Try to use ioremap function to map your physical address to logical (virtual) address and then try ioread() or iowrite() or __raw_readl() or __raw_writel() functions.

Please refer the following thread which has FPGA init code.

http://e2e.ti.com/support/embedded/linux/f/354/t/122942.aspx