Slowing down uPP transfer rate

Any help on this ?

Hey BAS,

  Not sure I follow your question, but if you want to "slow down" UPP transfers,  you can modify the UPPICR register (refer to Section 33.3.5 in SPRUH77A.pdf), specifcially bit 8 in this register.

  Hope this helps. Are you using Linux for your O/S on the OMAP?

Allan,

uPP I/O speeds up to 75 MHz with 8-16 bit data width per channel. I don't know the current speed of uPP in my system. As i mentioned earlier, it takes only 17 CPU cycle to transfer 1024 data point. I want to know how can I decrease the speed so that it takes more than 17 CPU cycle.

The specific bit you mentioned in UPICR register can be used to divide down the clock if channel A is used in TRANSMIT mode where as I am using channel A in RECEIVE mode.

I am using windows 7 for OMAP-L138.

Any help ?

Thanks.

BAS ,

a) Just reminding in case you missed . When the channel is configured in receive mode the CLOCK in not under control of UPP device .

     It is decided by PERIPHERAL DEVICE CLOCK. So in RECEIVE mode you have to slow the peripheral device which will in turn the UPP channel working 

     in receive mode .

b) Can you please let us know if you are using the default sample code available form TI or any thing else. 

    THIS IS BECAUSE I HAVE COMPLETED BUILDING THE DRIVER IN LINUX FOR THE SAME PERIPHERAL ,

    BUT NOW I AM SUPPOSED TO WORK FROM DSP SIDE .....on which i have never worked.

    So if you can please tell me from where you are using the sample  and how to compile it !!!!!!!!

Thanks

Ashish Mishra

[BANGLORE/INDIA]

Ashish Mishra,

a. Do you know how can I change Peripheral Device Clock to control the UPP clock ?

b. I am using BSL based UPP example code which can be found on Logic PD webpage.

Thanks.

Hi BAS, 

 As per my experience you cant control the clock of peripheral connected to UPP

 In case we are missing any point i would like to share my expr. 

1. I am having UPP connected to FPGA [XILINX]

2. Channel A is configured in TRANSMIT mode and Channel B in receive mode 

3. The clock frequency [Output clock]  of channel A is what i am controlling .

    In case of channel A transmitting , UPP acts like MASTER and FPGA acts like SLAVE.Slave will synchronize with master[UPP] clock. 

4. For channel B in RECEIVE mode , the clock of channel B is not under my control.It is Controlled by FPGA.

    Hence in RECEPTION mode FPGA acts like MASTER and UPP acts like SLAVE

5. Also in either case SLAVE will get 1/4th [Single Data Rate] or 1/8th [Double Data Rate] of MASTER clock

    Hence it the MASTER who have to control his clocking frequency. 

Hope it helps .Also if you think my understanding is wrong or i am missing , FEEL FREE TO CORRECT ME .................. 

Ashish Mishra

[BAnglore/India]