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C6748: EDMA missing interrupts

Christian Axtmann
Prodigy 110 points

Hi all,

i am currently trying to use the EDMA-Controller of the C6748 on our custom board in a non-BIOS application. The EDMA's future duty is to transfer data from the attached SDRAM on CS0 to an attached FPGA on CS4, both on the EMIFA (the FPGA supports a custom USB-connection, but imho that can be neglected). I startet out with the starterware-example which worked quite well. I adapted the example to a function that configures the DMA to transfer an arbitrary count of 32-Bit-Words from one point to another in 1kiB-blocks. If the data is not 1kiB-aligned, it uses a linked transfer (from channel 0 to channel 127) to transfer the rest of the data.

I have set the transfer-completion-event to interrupt 6 which reacts to the intermediate and final transfer-completion-event. But it seems, that sometimes the intermediate transmission-interrupt is omitted for no reason. That means, that my manually triggered transfer stops. By the way I should mention that there is a timer-generated interrupt on INT4 that is used for a real-time-control loop. When I disable that interrupt, the DMA works properly, but when it's enabled, the DMA stops from time to time. Is there any particular reason for that? In my opinion the DMA-interrupt at least should not get lost. I also tried to poll the IPR-register, but there is the same issue, sometimes there is no bit set, even though the corresponding array has been transferred.

If you need additional information, just write it. Because of readability, I didn't post my code. (By the way, is there a way to properly post code here? To get a decent indentation and so on)

Thanks,

Chris

 

 

 

 

 

  • 0
    Intellectual 960 points

    Did you ever solve this problem?  I'm having a similar issue with the EDMA missing the completion event from McBSP.

  • 0
    TI__Mastermind 35645 points

    Hi Chris,

    Thanks for your post.

    This issue is based out of system priority considerations. Basically, EDMA3 Transfer controller servicing audio/video/display threads typically have real-time deadlines should be programmed with highest priority compared to TC servicing memory to memory transfer requests.

    Each transfer controller on the EDMA3 device is actually a master peripheral and therefore, it is important to program the priority of each transfer controller with respect to each other and also with respect to other masters in the system. All master peripherals on the device have a programmable priority level. When multiple masters are trying to access common shared resources (slave memory or peripherals), this priority value allows the system interconnect to arbitrate requests from different masters based on their priority.

    In your case, a timer generated interrupt on INT4, typically had real-time deadlines and it is programmed with highest priority compared to other master peripheral (EDMA3 TC) servicing memory to memory transfer request, So the DMA manually triggered transfer stops from time to time and there cause the issue.

    The above priority assignment is determined in the Master Priority Registers (MSTPRI0-MSTPRI2) in the System Configuration Module, where each master has an allocated priority value (power on reset default value) which shall be reprogrammed based on the application prioritization.

    Based on this, I recommend you to refer Section 10.3 in the System Configuration (SYSCFG) Module of C6748 DSP's technical reference manual which is given below in order to re-program the master peripheral priority (EDMA3 TC in your case) to obtain the desired performance. Also, refer Section 16.2.14 & 16.2.13.4 for EDMA3 prioritization and EDMA3TC performance and system considerations in the below TRM.

    http://www.ti.com/lit/spruh79

    Note: The priority value can be configured between 0 to 7, with 0 being the highest priority and 7 being the lowest priority.

    Regards,

    Sivaraj K

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  • 0 in reply to Sivaraj Kuppuraj
    Intellectual 960 points

    Sivaraj,

    Thank you.  That makes sense.  I think I have a different application than you are thinking of...  I'm using the EDMA_0 to receive data from McBSP1, and also to send data over UART1.  The McBSP is higher priority, so I kept McBSP as Q0, and changed UART to Q1.  It didn't help.

    Then I switched the MSTRPI registers so that EDMA_0_TC0 is priority 0, EDMA_0_TC1 is priority 1.  I also switched the QUEPRI so that Q0 is priority 0 and Q1 is priority 1.  It seems to be working so far, but sometimes it takes a few hours for the system to fail.  I have my fingers crossed...

  • 0 in reply to Chris Roed
    TI__Mastermind 35645 points

    Hi Chris,

    Thanks for your post.

    This could be of some other issue. But basically, each master peripheral can be reprogrammed in the  Master Priority Registers (MSTPRI0-MSTPRI2) to assign an appropriate priority based on the application need and also the priority of each transfer controller's service requests. So that, DMA data transfer wouldn't be affected in any manner.

    Regards,

    Sivaraj K

    ---------------------------------------------------------------------------------
    Please click the     Verify Answer button on this post if it answers your question.
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  • 0 in reply to Sivaraj Kuppuraj
    Intellectual 960 points

    Sivaraj,  

    After changing the priority registers, I still had a failure after a few hours.  I may have found a fix though, but it's the ugliest solution that's ever been implemented.  In my main loop, I check the EDMA IPR, and if I see the McBSP_RX flag, I manually set the ISR bit for the EDMA interrupt.  I set it running last night and it's been running error free for over 16 hours now.

    Is there any way I can map the UART_1_TX event to EDMA_1?  Right now EDMA_1 is sitting idle.

    P.S, I would be verifying all of your answers, but I'm not the original poster on this forum and it seems that I don't have permission.  If I'm still having problems I will start a new thread.

  • 0 in reply to Chris Roed
    TI__Mastermind 35645 points

    Hi Chris,

    Thanks for your post.

    You can send data over UART1 using EDMA_1 instead of using same EDMA_0 to receive data from McBSP1 and also to send data over UART1. There are no issue in mapping UART1 to EDMA_1.

    Thanks & regards,

    Sivaraj K

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    Please click the     Verify Answer button on this post if it answers your question.
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  • 0 in reply to Sivaraj Kuppuraj
    Intellectual 960 points
    Hi Sivaraj,
    Its an older post, but i have a query here.
    You mentioned
    "You can send data over UART1 using EDMA_1 instead of using same EDMA_0 to receive data from McBSP1 and also to send data over UART1. There are no issue in mapping UART1 to EDMA_1."
    Is it possible?? If yes how to do that?
  • 0 in reply to Bhaskar Reddy
    Intellectual 960 points
    As per the data sheet Table 6-12. EDMA Synchronization Events, channel synchronization mapping is done among EDMA3 CC 0 and EDMA3 CC1. Can we changes.
  • 0 in reply to Bhaskar Reddy
    TI__Mastermind 35645 points

    Hi,

    You cannot change the mapping between peripheral events and DMA/QDMA channels among the EDMA CC's queue which is unique. The mapping is unique and we do not have control to change the events mapped to corresponding queue in the channel controller.

    Thanks & regards,

    Sivaraj K