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RSRCLR bit in GBCLTL of AM180x

Other Parts Discussed in Thread: AM1806

I am having a problem getting the serializer for McASP0 in the AM1806 to activate reliably.

Per the AM1806 documentation on the serializer prior to taking the serializer out of reset I set RSTAT=0xffff. The following is a code snippet:

HWREG(baseAddr + MCASP_RSTAT) = 0xFFFF;

/* Release transmit serializers from reset*/

HWREG(baseAddr + MCASP_GBLCTL) |= MCASP_GBLCTL_RSRCLR;
while((HWREG(baseAddr + MCASP_GBLCTL) & MCASP_GBLCTL_RSRCLR)

!= MCASP_GBLCTL_RSRCLR) ;

Problem is the code sometimes gets stuck in the while loop waiting for the RSRCLR bit to latch.

Most times the code works correctly and the bit is latched but about 20% of the time it is not and the code hangs here.

What would cause the RSRCLR bit to not latch? I assume the same problem is happening with the XSRCLR bit.