(OMAP-L137, DSP side)
With previous forum help (Thanks, Brad), I have debugged memory-to-memory transfers of 250000 16-bit words using an A-Synchronized transfer. I receive the transfer complete interrupt as expected. Note that this required the use of BCNT, BCNTRLD, and CCNT because of the large number of elements transfered.
Now I'm trying to get the SPI1-to-memory transfer configured. The A2D that I'm talking to via the SPI is the ADS8330. I have the EOC/INT line connected to a GPIO line. I am running the chip in 4-pin mode with chip select.
I've read in the DMA literature that I run the risk of starving a DMA and that I might want to chain the transmit and receive DMA transfers. This makes sense to me, but I'm not sure how to configure the events. The configuration for the memory-to-memory tests included a manual trigger event to start the transfer. The ADS8330 has an auto-trigger mode. It requires that I write the configuration register (0xe---). Then to receive the A2D data, I've got to transmit 0xd---. If I configure the A2D to drive the INT output, I can get a GPIO falling trigger event when the conversion completes. That is, when the falling trigger occurs, the SPI chip select/ SCLKs can be driven to clock in the received data/ transmit the next read command.
While I'm collecting the A2D SPI data into memory via DMA, I have a background task number-crunching on the previously-collected buffer. To avoid having an interrupt routine for each transfer impact the number-crunching any more than is necessary, I'd like the DMA transfers (SPI transmit/receive) to continue without much interaction.
To avoid receive overruns on the SPI data, I'll need to have the receive DMA transfer keep up with the transmit DMA transfer. Am I correct in assuming that this is a perfect case for chained DMA transfers? Is it true that I'll need to perform a transmit and receive transfer for each 16-bit data element?
The chained-transfers occur at intermediate completion events. I think that means that the chaining event would occur when BCNT is exhausted. Is that true? If so, does that mean that BCNT can't be larger than 1? (ACNT = 2)
Since the GPIO event is Event 29, does this mean that I need to set up one of the DMA transfers to PaRAM set 29? (Currently I'm using PaRAM sets 8 and 9 with receive on 8 and transmit on 9, but only manual SPI transfers are currently working...