AIC3106 + OMAPL137 ... Lag?

A quick glance of the aic3106_loop_xxx.c code code looks like a straight copy as you mention. 

In the data sheet slas509e.pdf available at: http://focus.ti.com/docs/prod/folders/print/tlv320aic3106.html , p. 8 mentions an ADC group delay of 17 and p. 10 mentions a DAC group delay of 21.  I think that adds up to the number of sample delay  you are seeing (if I am reading the units correctly). 

<3

It looks like that is it : )

Thank you.

On page 51 there is a configuration for the control register page0/register9 that seems to indicate that the group delay may be variable during operation.

On the other hand, "linear phase" should mean that I will be getting the same delay independent of the frequency of the signals.

So how do I have to see this? Are changes in the group delays "rare" and the configuration register is there just for safety reasons, or are such delays very regular?
How do these changes in group delay come about? And is there any way to predict by how much they will change?

EDIT Feel free to point me to pertinent books on the matter. I am obviously not very familiar with what is happening "behind the scenes" with these ADCs/DACs.

Good question.  I really don't know that specific on the data converters.

Have you tried posting on one of the TI Analog Forums?

I can confirm that there is some "jitter" on the group delay, i.e. the group delay changes from one reset of the CPU to another, and possibly even during the same run.

I have found out that the aforementioned Register 9 / Page 0 fixes this to some extent, or in other words: if the phase of the signal you are sampling is important to you, you want to set to 1 the D1 and D2 bits of this register (i.e. ADC/DAC Re-Sync), see slas509e page 51.

Robin.

Hi!

Even if i set bits D1 and D2 in register 9 i get jitter of group delay. As i suspect the range of this deviation of delay is within +-1/4 1/Fs.

Is there any ability to eliminate jitter at all?

As i understand aic3106 and mcASP clocked from one source crystal.... 

In pdf on page 51 :

D2 R/W 0 DAC Re-Sync
0: Don’t Care
1: Re-sync stereo DAC with codec interface if the group delay changes by more than ±DACFS/4.
D1 R/W 0 ADC Re-Sync
0: Don’t Care
1: Re-sync stereo ADC with codec interface if the group delay changes by more than ±ADCFS/4.

But what is ADCFS/4 ? Is this a time?  What is the mechanism of synchronization?

Have anybody additional information on this topic? Datasheet is poor... 

Thanks

Hello all,

I want to pick up the topic again and ask, if anybody has an idea how eliminate the jitter on the group delay.

I'm as well interested in a group delay that is as stable as possible.

Best regards,

Tobias

Hello.

After some time of experimentation i can also say that Register 9 / Page 0 fixes this jitter. Please, Try to set  bits D1 and D2. This synchronize analog clock and digital clock.  

Hello,

thank you for your qick reply. I tried it and the jitter becomes better, but not perfectly equal between several restarts (difference about 4 1/fs). As you seem to be very experienced with the device, I have another question:

I observed a strange behavior at line in, when I take a continuous signal as input. The attached picture shows the first 100 samples of the line in signal. Input is a pure sinusoid with 500 Hz. First of all the lag time is more than the 17/fs declared for the ADC. Secondly, there is a strange high frequency signal (about fs/2) which I cannot explain.
Have you ever obserced a similar behaviour or do you have a hint what the reason could be?

I would be glad if you can help me.

Best regards
Tobias

Tobias Brack

I observed a strange behavior at line in, when I take a continuous signal as input. The attached picture shows the first 100 samples of the line in signal. Input is a pure sinusoid with 500 Hz. First of all the lag time is more than the 17/fs declared for the ADC. Secondly, there is a strange high frequency signal (about fs/2) which I cannot explain. 

Have you ever obserced a similar behaviour or do you have a hint what the reason could be?

1. Can you describe the arrangement of your experiment in more details? Do you use external sine generator?

2. I saw this distortion at the sample beginning. I didn't deeply analyze this but think this connected with transients in the input digital filter of ADC.

Hello,

1. I have an external signal generator, providing the continuous signal. The output goes directly to LINE1L with an Amplitude of ca. 0.1Vpp. The output is already active, then the DSP code is started and the input is saved as a text file.
The code is based on one of the codes of the aic3106 test. (aic3106_loop_linein.c).

My application is similar to what Robin Vujanic has posted so time ago. The input, coming from an external system, is used in a control loop running on the DSP to regulate the output signal. The aim is to control the phase between in- and output. Therefore a constant phase shift due to the DSP is essential.

2. this was my guess too. I can handle the distortions at the beginning, but I guessed this could be related to the different lag times, what is very problematic for my application.

Currently I am working with fs=48kHz, probably it would be worth a try to go to 96kHz. Do you have experience with that?

Thanks for your held and best regards
Tobias

1. Unfortunately i am not introduced with sample you mean aic3106_loop_linein.c. As a suggestion, note that most likely this sample uses some input and output buffers (for ping pong). Perhaps you see this empty read buffer  + 17 samples at the beginning  of captured data?

2. I run ADC and mcASP at 24 kHz rate. Try ADC HIGH-PASS FILTER configuration (SLAS509E page 32). Maybe it is switched on? 

to 1. This is a good hint, I will try to find the place where the buffer is defined.
to 2. ADC Highpass is off.

FYI attached the files for the aic3106 test, that I took as a sample.

6064.aic3106.zip

Best regards
Tobias