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Understanding Timing Diagram of VPIF

  Hi,

   I wanted to understand certain terminologies used in Raw Capture Progressive Mode:

a. Vertical Blanking , min = 3lines                  ---------- Is it same as telling it needs a minimum of 3 rows

b. Horizontal Blanking, min = 21 clk              ---------- Is it same as telling it needs a minimum of 21 VP_CLK0 and 1 input clk or is it mentioned in number of rows.

c. Frame Blanking, min = 369 clk                   --------- ???????????????

d. Valid data period, min= 2 clk                      ---------- Why is it less than horizontal blanking period ? and what it is ?

Below is the timing diagram of Digital video port of OV2643

Also the master clock generated by CDCE913PW on UI board generates normal pulse of 24.0000080 Mhz

while VP_CLKIN0 and 1 are driven by 48 Mhz PCLK generated by camera module, its shape is saw tooth form.

Does the wave form shape of VP_CLKIN 0and 1 affect the VPIF ???

  •     

    Hi,

       I wanted to understand certain terminologies used in Raw Capture Progressive Mode:

    a. Vertical Blanking , min = 3lines                  ---------- Is it same as telling it needs a minimum of 3 rows

    b. Horizontal Blanking, min = 21 clk              ---------- Is it same as telling it needs a minimum of 21 VP_CLK0 and 1 input clk or is it mentioned in number of rows.

    c. Frame Blanking, min = 369 clk                   --------- ???????????????

    d. Valid data period, min= 2 clk                      ---------- Why is it less than horizontal blanking period ? and what it is ?

    Below is the timing diagram and timing specification for 720p of OV2643

      

      

      

    Also the master clock generated by CDCE913PW on UI board generates normal pulse of 24.0000080 Mhz

    while VP_CLKIN0 and 1 are driven by 48 Mhz PCLK generated by camera module, its shape is saw tooth form.

    Does the wave form shape of VP_CLKIN 0and 1 affect the VPIF ???

     

    But the VPIF document recommends the input clock for VP_CLKin0 and 1 to be 74.25 Mhz, is it  really necessary or is it  just fine to have 48 Mhz as clock input

  • Hi Vaishak,

    Thanks for your patience and apologize for the delayed response on this.

    Did you solve the problem ?

    If yes, could you share it with us and also it could help to other community members as well.

    If not, can we re-open the thread ?

    But the VPIF document recommends the input clock for VP_CLKin0 and 1 to be 74.25 Mhz, is it  really necessary or is it  just fine to have 48 Mhz as clock input

    Always we recommend to use clock that what datasheet says, so you have to proceed with 74.25MHz clock rate to meet VPIF requirements else you may get unexpected output could occur.

    Also the master clock generated by CDCE913PW on UI board generates normal pulse of 24.0000080 Mhz

    while VP_CLKIN0 and 1 are driven by 48 Mhz PCLK generated by camera module, its shape is saw tooth form.

    Why the camera sent SAW tooth waveform ?

    Is that normal behavior of camera and confirmed with camera vendor ?

  • Hi Stalin,

    I resolved the issue, I was able to get the image from the camera at 48 Mhz input to both clkin0 and 1 from camera hardware.

    There was no problem as such.

    I was just interested in understanding the timing diagram of the vpif port of OMAPL13X provided by TI.

    Thanks 

    Vaishak

  • Hi Vaishak,

    Thanks for your update.