Micron 32Gb NAND (MT29F32G08AFABAWP, with 4K page) "ECC error in BBT" on OMAP-L138

/*
 * NAND driver for TI DaVinci based boards.
 *
 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
 *
 * Based on Linux DaVinci NAND driver by TI. Original copyright follows:
 */

/*
 *
 * linux/drivers/mtd/nand/nand_davinci.c
 *
 * NAND Flash Driver
 *
 * Copyright (C) 2006 Texas Instruments.
 *
 * ----------------------------------------------------------------------------
 *
 * SPDX-License-Identifier:	GPL-2.0+
 *
 * ----------------------------------------------------------------------------
 *
 *  Overview:
 *   This is a device driver for the NAND flash device found on the
 *   DaVinci board which utilizes the Samsung k9k2g08 part.
 *
 Modifications:
 ver. 1.0: Feb 2005, Vinod/Sudhakar
 -
 */

#include <common.h>
#include <asm/io.h>
#include <nand.h>
#include <asm/arch/nand_defs.h>
#include <asm/arch/emif_defs.h>

/* Definitions for 4-bit hardware ECC */
#define NAND_TIMEOUT				10240
#define NAND_ECC_BUSY				0xC
#define NAND_4BITECC_MASK			0x03FF03FF
#define EMIF_NANDFSR_ECC_STATE_MASK	0x00000F00
#define ECC_STATE_NO_ERR			0x0
#define ECC_STATE_TOO_MANY_ERRS		0x1
#define ECC_STATE_ERR_CORR_COMP_P	0x2
#define ECC_STATE_ERR_CORR_COMP_N	0x3

/*
 * Exploit the little endianness of the ARM to do multi-byte transfers
 * per device read. This can perform over twice as quickly as individual
 * byte transfers when buffer alignment is conducive.
 *
 * NOTE: This only works if the NAND is not connected to the 2 LSBs of
 * the address bus. On Davinci EVM platforms this has always been true.
 */
static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
	struct nand_chip *chip = mtd->priv;
	const u32 *nand = chip->IO_ADDR_R;

	/* Make sure that buf is 32 bit aligned */
	if (((int)buf & 0x3) != 0) {
		if (((int)buf & 0x1) != 0) {
			if (len) {
				*buf = readb(nand);
				buf += 1;
				len--;
			}
		}

		if (((int)buf & 0x3) != 0) {
			if (len >= 2) {
				*(u16 *)buf = readw(nand);
				buf += 2;
				len -= 2;
			}
		}
	}

	/* copy aligned data */
	while (len >= 4) {
		*(u32 *)buf = __raw_readl(nand);
		buf += 4;
		len -= 4;
	}

	/* mop up any remaining bytes */
	if (len) {
		if (len >= 2) {
			*(u16 *)buf = readw(nand);
			buf += 2;
			len -= 2;
		}

		if (len)
			*buf = readb(nand);
	}
}

static void nand_davinci_write_buf(struct mtd_info *mtd, const uint8_t *buf,
				   int len)
{
	struct nand_chip *chip = mtd->priv;
	const u32 *nand = chip->IO_ADDR_W;

	/* Make sure that buf is 32 bit aligned */
	if (((int)buf & 0x3) != 0) {
		if (((int)buf & 0x1) != 0) {
			if (len) {
				writeb(*buf, nand);
				buf += 1;
				len--;
			}
		}

		if (((int)buf & 0x3) != 0) {
			if (len >= 2) {
				writew(*(u16 *)buf, nand);
				buf += 2;
				len -= 2;
			}
		}
	}

	/* copy aligned data */
	while (len >= 4) {
		__raw_writel(*(u32 *)buf, nand);
		buf += 4;
		len -= 4;
	}

	/* mop up any remaining bytes */
	if (len) {
		if (len >= 2) {
			writew(*(u16 *)buf, nand);
			buf += 2;
			len -= 2;
		}

		if (len)
			writeb(*buf, nand);
	}
}

static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
		unsigned int ctrl)
{
	struct		nand_chip *this = mtd->priv;
	u_int32_t	IO_ADDR_W = (u_int32_t)this->IO_ADDR_W;

	if (ctrl & NAND_CTRL_CHANGE) {
		IO_ADDR_W &= ~(MASK_ALE|MASK_CLE);

		if (ctrl & NAND_CLE)
			IO_ADDR_W |= MASK_CLE;
		if (ctrl & NAND_ALE)
			IO_ADDR_W |= MASK_ALE;
		this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
	}

	if (cmd != NAND_CMD_NONE)
		writeb(cmd, IO_ADDR_W);
}

#ifdef CONFIG_SYS_NAND_HW_ECC

static u_int32_t nand_davinci_readecc(struct mtd_info *mtd)
{
	u_int32_t	ecc = 0;

	ecc = __raw_readl(&(davinci_emif_regs->nandfecc[
				CONFIG_SYS_NAND_CS - 2]));

	return ecc;
}

static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
{
	u_int32_t	val;

	/* reading the ECC result register resets the ECC calculation */
	nand_davinci_readecc(mtd);

	val = __raw_readl(&davinci_emif_regs->nandfcr);
	val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
	val |= DAVINCI_NANDFCR_1BIT_ECC_START(CONFIG_SYS_NAND_CS);
	__raw_writel(val, &davinci_emif_regs->nandfcr);
}

static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
		u_char *ecc_code)
{
	u_int32_t		tmp;

	tmp = nand_davinci_readecc(mtd);

	/* Squeeze 4 bytes ECC into 3 bytes by removing RESERVED bits
	 * and shifting. RESERVED bits are 31 to 28 and 15 to 12. */
	tmp = (tmp & 0x00000fff) | ((tmp & 0x0fff0000) >> 4);

	/* Invert so that erased block ECC is correct */
	tmp = ~tmp;

	*ecc_code++ = tmp;
	*ecc_code++ = tmp >>  8;
	*ecc_code++ = tmp >> 16;

	/* NOTE:  the above code matches mainline Linux:
	 *	.PQR.stu ==> ~PQRstu
	 *
	 * MontaVista/TI kernels encode those bytes differently, use
	 * complicated (and allegedly sometimes-wrong) correction code,
	 * and usually shipped with U-Boot that uses software ECC:
	 *	.PQR.stu ==> PsQRtu
	 *
	 * If you need MV/TI compatible NAND I/O in U-Boot, it should
	 * be possible to (a) change the mangling above, (b) reverse
	 * that mangling in nand_davinci_correct_data() below.
	 */

	return 0;
}

static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat,
		u_char *read_ecc, u_char *calc_ecc)
{
	struct nand_chip *this = mtd->priv;
	u_int32_t ecc_nand = read_ecc[0] | (read_ecc[1] << 8) |
					  (read_ecc[2] << 16);
	u_int32_t ecc_calc = calc_ecc[0] | (calc_ecc[1] << 8) |
					  (calc_ecc[2] << 16);
	u_int32_t diff = ecc_calc ^ ecc_nand;

	if (diff) {
		if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
			/* Correctable error */
			if ((diff >> (12 + 3)) < this->ecc.size) {
				uint8_t find_bit = 1 << ((diff >> 12) & 7);
				uint32_t find_byte = diff >> (12 + 3);

				dat[find_byte] ^= find_bit;
				MTDDEBUG(MTD_DEBUG_LEVEL0, "Correcting single "
					 "bit ECC error at offset: %d, bit: "
					 "%d\n", find_byte, find_bit);
				return 1;
			} else {
				return -1;
			}
		} else if (!(diff & (diff - 1))) {
			/* Single bit ECC error in the ECC itself,
			   nothing to fix */
			MTDDEBUG(MTD_DEBUG_LEVEL0, "Single bit ECC error in "
				 "ECC.\n");
			return 1;
		} else {
			/* Uncorrectable error */
			MTDDEBUG(MTD_DEBUG_LEVEL0, "ECC UNCORRECTED_ERROR 1\n");
			return -1;
		}
	}
	return 0;
}
#endif /* CONFIG_SYS_NAND_HW_ECC */

#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = {
#if defined(CONFIG_SYS_NAND_PAGE_2K)
	.eccbytes = 40,
#ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC
	.eccpos = {
		6,   7,  8,  9, 10,	11, 12, 13, 14, 15,
		22, 23, 24, 25, 26,	27, 28, 29, 30, 31,
		38, 39, 40, 41, 42,	43, 44, 45, 46, 47,
		54, 55, 56, 57, 58,	59, 60, 61, 62, 63,
	},
	.oobfree = {
		{2, 4}, {16, 6}, {32, 6}, {48, 6},
	},
#else
	.eccpos = {
		24, 25, 26, 27, 28,
		29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
		39, 40, 41, 42, 43, 44, 45, 46, 47, 48,
		49, 50, 51, 52, 53, 54, 55, 56, 57, 58,
		59, 60, 61, 62, 63,
		},
	.oobfree = {
		{.offset = 2, .length = 22, },
	},
#endif	/* #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC */
#elif defined(CONFIG_SYS_NAND_PAGE_4K)
	.eccbytes = 80,
	.eccpos = {
		48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
		58, 59, 60, 61, 62, 63,	64, 65, 66, 67,
		68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
		78, 79,	80, 81, 82, 83,	84, 85, 86, 87,
		88, 89, 90, 91, 92, 93,	94, 95, 96, 97,
		98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
		108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
		118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
		},
	.oobfree = {
		{.offset = 2, .length = 46, },
	},
#endif
};

static void nand_davinci_4bit_enable_hwecc(struct mtd_info *mtd, int mode)
{
	u32 val;

	switch (mode) {
	case NAND_ECC_WRITE:
	case NAND_ECC_READ:
		/*
		 * Start a new ECC calculation for reading or writing 512 bytes
		 * of data.
		 */
		val = __raw_readl(&davinci_emif_regs->nandfcr);
		val &= ~DAVINCI_NANDFCR_4BIT_ECC_SEL_MASK;
		val |= DAVINCI_NANDFCR_NAND_ENABLE(CONFIG_SYS_NAND_CS);
		val |= DAVINCI_NANDFCR_4BIT_ECC_SEL(CONFIG_SYS_NAND_CS);
		val |= DAVINCI_NANDFCR_4BIT_ECC_START;
		__raw_writel(val, &davinci_emif_regs->nandfcr);
		break;
	case NAND_ECC_READSYN:
		val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]);
		break;
	default:
		break;
	}
}

static u32 nand_davinci_4bit_readecc(struct mtd_info *mtd, unsigned int ecc[4])
{
	int i;

	for (i = 0; i < 4; i++) {
		ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) &
			NAND_4BITECC_MASK;
	}

	return 0;
}

static int nand_davinci_4bit_calculate_ecc(struct mtd_info *mtd,
					   const uint8_t *dat,
					   uint8_t *ecc_code)
{
	unsigned int hw_4ecc[4];
	unsigned int i;

	nand_davinci_4bit_readecc(mtd, hw_4ecc);

	/*Convert 10 bit ecc value to 8 bit */
	for (i = 0; i < 2; i++) {
		unsigned int hw_ecc_low = hw_4ecc[i * 2];
		unsigned int hw_ecc_hi = hw_4ecc[(i * 2) + 1];

		/* Take first 8 bits from val1 (count1=0) or val5 (count1=1) */
		*ecc_code++ = hw_ecc_low & 0xFF;

		/*
		 * Take 2 bits as LSB bits from val1 (count1=0) or val5
		 * (count1=1) and 6 bits from val2 (count1=0) or
		 * val5 (count1=1)
		 */
		*ecc_code++ =
		    ((hw_ecc_low >> 8) & 0x3) | ((hw_ecc_low >> 14) & 0xFC);

		/*
		 * Take 4 bits from val2 (count1=0) or val5 (count1=1) and
		 * 4 bits from val3 (count1=0) or val6 (count1=1)
		 */
		*ecc_code++ =
		    ((hw_ecc_low >> 22) & 0xF) | ((hw_ecc_hi << 4) & 0xF0);

		/*
		 * Take 6 bits from val3(count1=0) or val6 (count1=1) and
		 * 2 bits from val4 (count1=0) or  val7 (count1=1)
		 */
		*ecc_code++ =
		    ((hw_ecc_hi >> 4) & 0x3F) | ((hw_ecc_hi >> 10) & 0xC0);

		/* Take 8 bits from val4 (count1=0) or val7 (count1=1) */
		*ecc_code++ = (hw_ecc_hi >> 18) & 0xFF;
	}

	return 0;
}

static int nand_davinci_4bit_correct_data(struct mtd_info *mtd, uint8_t *dat,
					  uint8_t *read_ecc, uint8_t *calc_ecc)
{
	int i;
	unsigned int hw_4ecc[4];
	unsigned int iserror;
	unsigned short *ecc16;
	unsigned int numerrors, erroraddress, errorvalue;
	u32 val;

	/*
	 * Check for an ECC where all bytes are 0xFF.  If this is the case, we
	 * will assume we are looking at an erased page and we should ignore
	 * the ECC.
	 */
	for (i = 0; i < 10; i++) {
		if (read_ecc[i] != 0xFF)
			break;
	}
	if (i == 10)
		return 0;

	/* Convert 8 bit in to 10 bit */
	ecc16 = (unsigned short *)&read_ecc[0];

	/*
	 * Write the parity values in the NAND Flash 4-bit ECC Load register.
	 * Write each parity value one at a time starting from 4bit_ecc_val8
	 * to 4bit_ecc_val1.
	 */

	/*Take 2 bits from 8th byte and 8 bits from 9th byte */
	__raw_writel(((ecc16[4]) >> 6) & 0x3FF,
			&davinci_emif_regs->nand4biteccload);

	/* Take 4 bits from 7th byte and 6 bits from 8th byte */
	__raw_writel((((ecc16[3]) >> 12) & 0xF) | ((((ecc16[4])) << 4) & 0x3F0),
			&davinci_emif_regs->nand4biteccload);

	/* Take 6 bits from 6th byte and 4 bits from 7th byte */
	__raw_writel((ecc16[3] >> 2) & 0x3FF,
			&davinci_emif_regs->nand4biteccload);

	/* Take 8 bits from 5th byte and 2 bits from 6th byte */
	__raw_writel(((ecc16[2]) >> 8) | ((((ecc16[3])) << 8) & 0x300),
			&davinci_emif_regs->nand4biteccload);

	/*Take 2 bits from 3rd byte and 8 bits from 4th byte */
	__raw_writel((((ecc16[1]) >> 14) & 0x3) | ((((ecc16[2])) << 2) & 0x3FC),
			&davinci_emif_regs->nand4biteccload);

	/* Take 4 bits form 2nd bytes and 6 bits from 3rd bytes */
	__raw_writel(((ecc16[1]) >> 4) & 0x3FF,
			&davinci_emif_regs->nand4biteccload);

	/* Take 6 bits from 1st byte and 4 bits from 2nd byte */
	__raw_writel((((ecc16[0]) >> 10) & 0x3F) | (((ecc16[1]) << 6) & 0x3C0),
			&davinci_emif_regs->nand4biteccload);

	/* Take 10 bits from 0th and 1st bytes */
	__raw_writel((ecc16[0]) & 0x3FF,
			&davinci_emif_regs->nand4biteccload);

	/*
	 * Perform a dummy read to the EMIF Revision Code and Status register.
	 * This is required to ensure time for syndrome calculation after
	 * writing the ECC values in previous step.
	 */

	val = __raw_readl(&davinci_emif_regs->nandfsr);

	/*
	 * Read the syndrome from the NAND Flash 4-Bit ECC 1-4 registers.
	 * A syndrome value of 0 means no bit errors. If the syndrome is
	 * non-zero then go further otherwise return.
	 */
	nand_davinci_4bit_readecc(mtd, hw_4ecc);

	if (!(hw_4ecc[0] | hw_4ecc[1] | hw_4ecc[2] | hw_4ecc[3]))
		return 0;

	/*
	 * Clear any previous address calculation by doing a dummy read of an
	 * error address register.
	 */
	val = __raw_readl(&davinci_emif_regs->nanderradd1);

	/*
	 * Set the addr_calc_st bit(bit no 13) in the NAND Flash Control
	 * register to 1.
	 */
	__raw_writel(DAVINCI_NANDFCR_4BIT_CALC_START,
			&davinci_emif_regs->nandfcr);

	/*
	 * Wait for the corr_state field (bits 8 to 11) in the
	 * NAND Flash Status register to be not equal to 0x0, 0x1, 0x2, or 0x3.
	 * Otherwise ECC calculation has not even begun and the next loop might
	 * fail because of a false positive!
	 */
	i = NAND_TIMEOUT;
	do {
		val = __raw_readl(&davinci_emif_regs->nandfsr);
		val &= 0xc00;
		i--;
	} while ((i > 0) && !val);

	/*
	 * Wait for the corr_state field (bits 8 to 11) in the
	 * NAND Flash Status register to be equal to 0x0, 0x1, 0x2, or 0x3.
	 */
	i = NAND_TIMEOUT;
	do {
		val = __raw_readl(&davinci_emif_regs->nandfsr);
		val &= 0xc00;
		i--;
	} while ((i > 0) && val);

	iserror = __raw_readl(&davinci_emif_regs->nandfsr);
	iserror &= EMIF_NANDFSR_ECC_STATE_MASK;
	iserror = iserror >> 8;

	/*
	 * ECC_STATE_TOO_MANY_ERRS (0x1) means errors cannot be
	 * corrected (five or more errors).  The number of errors
	 * calculated (err_num field) differs from the number of errors
	 * searched.  ECC_STATE_ERR_CORR_COMP_P (0x2) means error
	 * correction complete (errors on bit 8 or 9).
	 * ECC_STATE_ERR_CORR_COMP_N (0x3) means error correction
	 * complete (error exists).
	 */

	if (iserror == ECC_STATE_NO_ERR) {
		val = __raw_readl(&davinci_emif_regs->nanderrval1);
		return 0;
	} else if (iserror == ECC_STATE_TOO_MANY_ERRS) {
		val = __raw_readl(&davinci_emif_regs->nanderrval1);
		return -1;
	}

	numerrors = ((__raw_readl(&davinci_emif_regs->nandfsr) >> 16)
			& 0x3) + 1;

	/* Read the error address, error value and correct */
	for (i = 0; i < numerrors; i++) {
		if (i > 1) {
			erroraddress =
			    ((__raw_readl(&davinci_emif_regs->nanderradd2) >>
			      (16 * (i & 1))) & 0x3FF);
			erroraddress = ((512 + 7) - erroraddress);
			errorvalue =
			    ((__raw_readl(&davinci_emif_regs->nanderrval2) >>
			      (16 * (i & 1))) & 0xFF);
		} else {
			erroraddress =
			    ((__raw_readl(&davinci_emif_regs->nanderradd1) >>
			      (16 * (i & 1))) & 0x3FF);
			erroraddress = ((512 + 7) - erroraddress);
			errorvalue =
			    ((__raw_readl(&davinci_emif_regs->nanderrval1) >>
			      (16 * (i & 1))) & 0xFF);
		}
		/* xor the corrupt data with error value */
		if (erroraddress < 512)
			dat[erroraddress] ^= errorvalue;
	}

	return numerrors;
}
#endif /* CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST */

static int nand_davinci_dev_ready(struct mtd_info *mtd)
{
#ifdef CONFIG_MACH_ELCOM_OMAPL138_CPUIP
	return (readl((u32 *)GPIO_BANK0_REG_INDATA_ADDR) & (1 << 15));
#else
	return __raw_readl(&davinci_emif_regs->nandfsr) & 0x1;
#endif
}

static void nand_flash_init(void)
{
	/* This is for DM6446 EVM and *very* similar.  DO NOT GROW THIS!
	 * Instead, have your board_init() set EMIF timings, based on its
	 * knowledge of the clocks and what devices are hooked up ... and
	 * don't even do that unless no UBL handled it.
	 */
#ifdef CONFIG_SOC_DM644X
	u_int32_t	acfg1 = 0x3ffffffc;

	/*------------------------------------------------------------------*
	 *  NAND FLASH CHIP TIMEOUT @ 459 MHz                               *
	 *                                                                  *
	 *  AEMIF.CLK freq   = PLL1/6 = 459/6 = 76.5 MHz                    *
	 *  AEMIF.CLK period = 1/76.5 MHz = 13.1 ns                         *
	 *                                                                  *
	 *------------------------------------------------------------------*/
	 acfg1 = 0
		| (0 << 31)	/* selectStrobe */
		| (0 << 30)	/* extWait */
		| (1 << 26)	/* writeSetup	10 ns */
		| (3 << 20)	/* writeStrobe	40 ns */
		| (1 << 17)	/* writeHold	10 ns */
		| (1 << 13)	/* readSetup	10 ns */
		| (5 << 7)	/* readStrobe	60 ns */
		| (1 << 4)	/* readHold	10 ns */
		| (3 << 2)	/* turnAround	?? ns */
		| (0 << 0)	/* asyncSize	8-bit bus */
		;

	__raw_writel(acfg1, &davinci_emif_regs->ab1cr); /* CS2 */

	/* NAND flash on CS2 */
	__raw_writel(0x00000101, &davinci_emif_regs->nandfcr);
#endif
}

void davinci_nand_init(struct nand_chip *nand)
{
	nand->chip_delay  = 0;
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
	nand->bbt_options  |= NAND_BBT_USE_FLASH;
#endif
#ifdef CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
	nand->options  |= NAND_NO_SUBPAGE_WRITE;
#endif
#ifdef CONFIG_SYS_NAND_HW_ECC
	nand->ecc.mode = NAND_ECC_HW;
	nand->ecc.size = 512;
	nand->ecc.bytes = 3;
	nand->ecc.strength = 1;
	nand->ecc.calculate = nand_davinci_calculate_ecc;
	nand->ecc.correct  = nand_davinci_correct_data;
	nand->ecc.hwctl  = nand_davinci_enable_hwecc;
#else
	nand->ecc.mode = NAND_ECC_SOFT;
#endif /* CONFIG_SYS_NAND_HW_ECC */
#ifdef CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
	nand->ecc.mode = NAND_ECC_HW_OOB_FIRST;
	nand->ecc.size = 512;
	nand->ecc.bytes = 10;
	nand->ecc.strength = 4;
	nand->ecc.calculate = nand_davinci_4bit_calculate_ecc;
	nand->ecc.correct = nand_davinci_4bit_correct_data;
	nand->ecc.hwctl = nand_davinci_4bit_enable_hwecc;
	nand->ecc.layout = &nand_davinci_4bit_layout_oobfirst;
#endif
	/* Set address of hardware control function */
	nand->cmd_ctrl = nand_davinci_hwcontrol;

	nand->read_buf = nand_davinci_read_buf;
	nand->write_buf = nand_davinci_write_buf;

	nand->dev_ready = nand_davinci_dev_ready;

	nand_flash_init();
}

#if defined(CONFIG_MACH_ELCOM_OMAPL138_CPUIP) || defined(CONFIG_MACH_ELCOM_OMAPL138_IVIS)
static void nand_cpuip_select_chip(struct mtd_info *mtd, int chip)
{
	struct nand_chip *this = mtd->priv;
	unsigned long wbase = (unsigned long) this->IO_ADDR_W;
	unsigned long rbase = (unsigned long) this->IO_ADDR_R;

	if (chip == 1) {
		__set_bit(14, &wbase);
		__set_bit(14, &rbase);
	} else {
		__clear_bit(14, &wbase);
		__clear_bit(14, &rbase);
	}
	this->IO_ADDR_W = (void *)wbase;
	this->IO_ADDR_R = (void *)rbase;
}
#endif

int board_nand_init(struct nand_chip *chip) __attribute__((weak));

int board_nand_init(struct nand_chip *chip)
{
	davinci_nand_init(chip);
#ifdef CONFIG_MACH_ELCOM_OMAPL138_CPUIP
	chip->select_chip = nand_cpuip_select_chip;
#endif
	return 0;
}

/*
 * davinci_nand.c - NAND Flash Driver for DaVinci family chips
 *
 * Copyright © 2006 Texas Instruments.
 *
 * Port to 2.6.23 Copyright © 2008 by:
 *   Sander Huijsen <Shuijsen@optelecom-nkf.com>
 *   Troy Kisky <troy.kisky@boundarydevices.com>
 *   Dirk Behme <Dirk.Behme@gmail.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/partitions.h>
#include <linux/slab.h>
#include <linux/gpio.h>

#include <mach/nand.h>
#include <mach/aemif.h>

#include <asm/mach-types.h>


/*
 * This is a device driver for the NAND flash controller found on the
 * various DaVinci family chips.  It handles up to four SoC chipselects,
 * and some flavors of secondary chipselect (e.g. based on A12) as used
 * with multichip packages.
 *
 * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
 * available on chips like the DM355 and OMAP-L137 and needed with the
 * more error-prone MLC NAND chips.
 *
 * This driver assumes EM_WAIT connects all the NAND devices' RDY/nBUSY
 * outputs in a "wire-AND" configuration, with no per-chip signals.
 */
struct davinci_nand_info {
	struct mtd_info		mtd;
	struct nand_chip	chip;
	struct nand_ecclayout	ecclayout;

	struct device		*dev;
	struct clk		*clk;
	bool			partitioned;

	bool			is_readmode;

	void __iomem		*base;
	void __iomem		*vaddr;

	uint32_t		ioaddr;
	uint32_t		current_cs;

	uint32_t		mask_chipsel;
	uint32_t		mask_ale;
	uint32_t		mask_cle;

	uint32_t		core_chipsel;

	struct davinci_aemif_timing	*timing;
};

static DEFINE_SPINLOCK(davinci_nand_lock);
static bool ecc4_busy;

#define to_davinci_nand(m) container_of(m, struct davinci_nand_info, mtd)


static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info,
		int offset)
{
	return __raw_readl(info->base + offset);
}

static inline void davinci_nand_writel(struct davinci_nand_info *info,
		int offset, unsigned long value)
{
	__raw_writel(value, info->base + offset);
}

/*----------------------------------------------------------------------*/

/*
 * Access to hardware control lines:  ALE, CLE, secondary chipselect.
 */

static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
				   unsigned int ctrl)
{
	struct davinci_nand_info	*info = to_davinci_nand(mtd);
	uint32_t			addr = info->current_cs;
	struct nand_chip		*nand = mtd->priv;

	/* Did the control lines change? */
	if (ctrl & NAND_CTRL_CHANGE) {
		if ((ctrl & NAND_CTRL_CLE) == NAND_CTRL_CLE)
			addr |= info->mask_cle;
		else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE)
			addr |= info->mask_ale;

		nand->IO_ADDR_W = (void __iomem __force *)addr;
	}

	if (cmd != NAND_CMD_NONE)
		iowrite8(cmd, nand->IO_ADDR_W);
}

static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
{
	struct davinci_nand_info	*info = to_davinci_nand(mtd);
	uint32_t			addr = info->ioaddr;

	/* maybe kick in a second chipselect */
	if (chip > 0)
		addr |= info->mask_chipsel;
	info->current_cs = addr;

	info->chip.IO_ADDR_W = (void __iomem __force *)addr;
	info->chip.IO_ADDR_R = info->chip.IO_ADDR_W;
}

/*----------------------------------------------------------------------*/

/*
 * 1-bit hardware ECC ... context maintained for each core chipselect
 */

static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd)
{
	struct davinci_nand_info *info = to_davinci_nand(mtd);

	return davinci_nand_readl(info, NANDF1ECC_OFFSET
			+ 4 * info->core_chipsel);
}

static void nand_davinci_hwctl_1bit(struct mtd_info *mtd, int mode)
{
	struct davinci_nand_info *info;
	uint32_t nandcfr;
	unsigned long flags;

	info = to_davinci_nand(mtd);

	/* Reset ECC hardware */
	nand_davinci_readecc_1bit(mtd);

	spin_lock_irqsave(&davinci_nand_lock, flags);

	/* Restart ECC hardware */
	nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET);
	nandcfr |= BIT(8 + info->core_chipsel);
	davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr);

	spin_unlock_irqrestore(&davinci_nand_lock, flags);
}

/*
 * Read hardware ECC value and pack into three bytes
 */
static int nand_davinci_calculate_1bit(struct mtd_info *mtd,
				      const u_char *dat, u_char *ecc_code)
{
	unsigned int ecc_val = nand_davinci_readecc_1bit(mtd);
	unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4);

	/* invert so that erased block ecc is correct */
	ecc24 = ~ecc24;
	ecc_code[0] = (u_char)(ecc24);
	ecc_code[1] = (u_char)(ecc24 >> 8);
	ecc_code[2] = (u_char)(ecc24 >> 16);

	return 0;
}

static int nand_davinci_correct_1bit(struct mtd_info *mtd, u_char *dat,
				     u_char *read_ecc, u_char *calc_ecc)
{
	struct nand_chip *chip = mtd->priv;
	uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) |
					  (read_ecc[2] << 16);
	uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) |
					  (calc_ecc[2] << 16);
	uint32_t diff = eccCalc ^ eccNand;

	if (diff) {
		if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
			/* Correctable error */
			if ((diff >> (12 + 3)) < chip->ecc.size) {
				dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7);
				return 1;
			} else {
				return -1;
			}
		} else if (!(diff & (diff - 1))) {
			/* Single bit ECC error in the ECC itself,
			 * nothing to fix */
			return 1;
		} else {
			/* Uncorrectable error */
			return -1;
		}

	}
	return 0;
}

/*----------------------------------------------------------------------*/

/*
 * 4-bit hardware ECC ... context maintained over entire AEMIF
 *
 * This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME
 * since that forces use of a problematic "infix OOB" layout.
 * Among other things, it trashes manufacturer bad block markers.
 * Also, and specific to this hardware, it ECC-protects the "prepad"
 * in the OOB ... while having ECC protection for parts of OOB would
 * seem useful, the current MTD stack sometimes wants to update the
 * OOB without recomputing ECC.
 */

static void nand_davinci_hwctl_4bit(struct mtd_info *mtd, int mode)
{
	struct davinci_nand_info *info = to_davinci_nand(mtd);
	unsigned long flags;
	u32 val;

	spin_lock_irqsave(&davinci_nand_lock, flags);

	/* Start 4-bit ECC calculation for read/write */
	val = davinci_nand_readl(info, NANDFCR_OFFSET);
	val &= ~(0x03 << 4);
	val |= (info->core_chipsel << 4) | BIT(12);
	davinci_nand_writel(info, NANDFCR_OFFSET, val);

	info->is_readmode = (mode == NAND_ECC_READ);

	spin_unlock_irqrestore(&davinci_nand_lock, flags);
}

/* Read raw ECC code after writing to NAND. */
static void
nand_davinci_readecc_4bit(struct davinci_nand_info *info, u32 code[4])
{
	const u32 mask = 0x03ff03ff;

	code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask;
	code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask;
	code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask;
	code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask;
}

/* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */
static int nand_davinci_calculate_4bit(struct mtd_info *mtd,
		const u_char *dat, u_char *ecc_code)
{
	struct davinci_nand_info *info = to_davinci_nand(mtd);
	u32 raw_ecc[4], *p;
	unsigned i;

	/* After a read, terminate ECC calculation by a dummy read
	 * of some 4-bit ECC register.  ECC covers everything that
	 * was read; correct() just uses the hardware state, so
	 * ecc_code is not needed.
	 */
	if (info->is_readmode) {
		davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
		return 0;
	}

	/* Pack eight raw 10-bit ecc values into ten bytes, making
	 * two passes which each convert four values (in upper and
	 * lower halves of two 32-bit words) into five bytes.  The
	 * ROM boot loader uses this same packing scheme.
	 */
	nand_davinci_readecc_4bit(info, raw_ecc);
	for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
		*ecc_code++ =   p[0]        & 0xff;
		*ecc_code++ = ((p[0] >>  8) & 0x03) | ((p[0] >> 14) & 0xfc);
		*ecc_code++ = ((p[0] >> 22) & 0x0f) | ((p[1] <<  4) & 0xf0);
		*ecc_code++ = ((p[1] >>  4) & 0x3f) | ((p[1] >> 10) & 0xc0);
		*ecc_code++ =  (p[1] >> 18) & 0xff;
	}

	return 0;
}

/* Correct up to 4 bits in data we just read, using state left in the
 * hardware plus the ecc_code computed when it was first written.
 */
static int nand_davinci_correct_4bit(struct mtd_info *mtd,
		u_char *data, u_char *ecc_code, u_char *null)
{
	int i;
	struct davinci_nand_info *info = to_davinci_nand(mtd);
	unsigned short ecc10[8];
	unsigned short *ecc16;
	u32 syndrome[4];
	u32 ecc_state;
	unsigned num_errors, corrected;
	unsigned long timeo;

	/* All bytes 0xff?  It's an erased page; ignore its ECC. */
	for (i = 0; i < 10; i++) {
		if (ecc_code[i] != 0xff)
			goto compare;
	}
	return 0;

compare:
	/* Unpack ten bytes into eight 10 bit values.  We know we're
	 * little-endian, and use type punning for less shifting/masking.
	 */
	if (WARN_ON(0x01 & (unsigned) ecc_code))
		return -EINVAL;
	ecc16 = (unsigned short *)ecc_code;

	ecc10[0] =  (ecc16[0] >>  0) & 0x3ff;
	ecc10[1] = ((ecc16[0] >> 10) & 0x3f) | ((ecc16[1] << 6) & 0x3c0);
	ecc10[2] =  (ecc16[1] >>  4) & 0x3ff;
	ecc10[3] = ((ecc16[1] >> 14) & 0x3)  | ((ecc16[2] << 2) & 0x3fc);
	ecc10[4] =  (ecc16[2] >>  8)         | ((ecc16[3] << 8) & 0x300);
	ecc10[5] =  (ecc16[3] >>  2) & 0x3ff;
	ecc10[6] = ((ecc16[3] >> 12) & 0xf)  | ((ecc16[4] << 4) & 0x3f0);
	ecc10[7] =  (ecc16[4] >>  6) & 0x3ff;

	/* Tell ECC controller about the expected ECC codes. */
	for (i = 7; i >= 0; i--)
		davinci_nand_writel(info, NAND_4BIT_ECC_LOAD_OFFSET, ecc10[i]);

	/* Allow time for syndrome calculation ... then read it.
	 * A syndrome of all zeroes 0 means no detected errors.
	 */
	davinci_nand_readl(info, NANDFSR_OFFSET);
	nand_davinci_readecc_4bit(info, syndrome);
	if (!(syndrome[0] | syndrome[1] | syndrome[2] | syndrome[3]))
		return 0;

	/*
	 * Clear any previous address calculation by doing a dummy read of an
	 * error address register.
	 */
	davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET);

	/* Start address calculation, and wait for it to complete.
	 * We _could_ start reading more data while this is working,
	 * to speed up the overall page read.
	 */
	davinci_nand_writel(info, NANDFCR_OFFSET,
			davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13));

	/*
	 * ECC_STATE field reads 0x3 (Error correction complete) immediately
	 * after setting the 4BITECC_ADD_CALC_START bit. So if you immediately
	 * begin trying to poll for the state, you may fall right out of your
	 * loop without any of the correction calculations having taken place.
	 * The recommendation from the hardware team is to initially delay as
	 * long as ECC_STATE reads less than 4. After that, ECC HW has entered
	 * correction state.
	 */
	timeo = jiffies + usecs_to_jiffies(100);
	do {
		ecc_state = (davinci_nand_readl(info,
				NANDFSR_OFFSET) >> 8) & 0x0f;
		cpu_relax();
	} while ((ecc_state < 4) && time_before(jiffies, timeo));

	for (;;) {
		u32	fsr = davinci_nand_readl(info, NANDFSR_OFFSET);

		switch ((fsr >> 8) & 0x0f) {
		case 0:		/* no error, should not happen */
			davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
			return 0;
		case 1:		/* five or more errors detected */
			davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
			return -EIO;
		case 2:		/* error addresses computed */
		case 3:
			num_errors = 1 + ((fsr >> 16) & 0x03);
			goto correct;
		default:	/* still working on it */
			cpu_relax();
			continue;
		}
	}

correct:
	/* correct each error */
	for (i = 0, corrected = 0; i < num_errors; i++) {
		int error_address, error_value;

		if (i > 1) {
			error_address = davinci_nand_readl(info,
						NAND_ERR_ADD2_OFFSET);
			error_value = davinci_nand_readl(info,
						NAND_ERR_ERRVAL2_OFFSET);
		} else {
			error_address = davinci_nand_readl(info,
						NAND_ERR_ADD1_OFFSET);
			error_value = davinci_nand_readl(info,
						NAND_ERR_ERRVAL1_OFFSET);
		}

		if (i & 1) {
			error_address >>= 16;
			error_value >>= 16;
		}
		error_address &= 0x3ff;
		error_address = (512 + 7) - error_address;

		if (error_address < 512) {
			data[error_address] ^= error_value;
			corrected++;
		}
	}

	return corrected;
}

/*----------------------------------------------------------------------*/

/*
 * NOTE:  NAND boot requires ALE == EM_A[1], CLE == EM_A[2], so that's
 * how these chips are normally wired.  This translates to both 8 and 16
 * bit busses using ALE == BIT(3) in byte addresses, and CLE == BIT(4).
 *
 * For now we assume that configuration, or any other one which ignores
 * the two LSBs for NAND access ... so we can issue 32-bit reads/writes
 * and have that transparently morphed into multiple NAND operations.
 */
static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
{
	struct nand_chip *chip = mtd->priv;

	if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
		ioread32_rep(chip->IO_ADDR_R, buf, len >> 2);
	else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
		ioread16_rep(chip->IO_ADDR_R, buf, len >> 1);
	else
		ioread8_rep(chip->IO_ADDR_R, buf, len);
}

static void nand_davinci_write_buf(struct mtd_info *mtd,
		const uint8_t *buf, int len)
{
	struct nand_chip *chip = mtd->priv;

	if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
		iowrite32_rep(chip->IO_ADDR_R, buf, len >> 2);
	else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
		iowrite16_rep(chip->IO_ADDR_R, buf, len >> 1);
	else
		iowrite8_rep(chip->IO_ADDR_R, buf, len);
}

/*
 * Check hardware register for wait status. Returns 1 if device is ready,
 * 0 if it is still busy.
 */
static int nand_davinci_dev_ready(struct mtd_info *mtd)
{
	struct davinci_nand_info *info = to_davinci_nand(mtd);
	#ifdef CONFIG_MACH_CODAS_OMAPL138_CPU_IP
	#define GPIO_NAND_RB	GPIO_TO_PIN(0, 15)

	return gpio_get_value(GPIO_NAND_RB) & BIT(15);
	#else
	return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0);
	#endif
}

/*----------------------------------------------------------------------*/

/* An ECC layout for using 4-bit ECC with small-page flash, storing
 * ten ECC bytes plus the manufacturer's bad block marker byte, and
 * and not overlapping the default BBT markers.
 */
static struct nand_ecclayout hwecc4_small __initconst = {
	.eccbytes = 10,
	.eccpos = { 0, 1, 2, 3, 4,
		/* offset 5 holds the badblock marker */
		6, 7,
		13, 14, 15, },
	.oobfree = {
		{.offset = 8, .length = 5, },
		{.offset = 16, },
	},
};

/* An ECC layout for using 4-bit ECC with large-page (2048bytes) flash,
 * storing ten ECC bytes plus the manufacturer's bad block marker byte,
 * and not overlapping the default BBT markers.
 */
static struct nand_ecclayout hwecc4_2048 __initconst = {
	.eccbytes = 40,
	.eccpos = {
		/* at the end of spare sector */
		24, 25, 26, 27, 28, 29,	30, 31, 32, 33,
		34, 35, 36, 37, 38, 39,	40, 41, 42, 43,
		44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
		54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
		},
	.oobfree = {
		/* 2 bytes at offset 0 hold manufacturer badblock markers */
		{.offset = 2, .length = 22, },
		/* 5 bytes at offset 8 hold BBT markers */
		/* 8 bytes at offset 16 hold JFFS2 clean markers */
	},
};

/* An ECC layout for using 4-bit ECC with large-page (4096bytes) flash,
 * storing ten ECC bytes plus the manufacturer's bad block marker byte,
 * and not overlapping the default BBT markers.
 */
static struct nand_ecclayout hwecc4_4096 __initconst = {
	.eccbytes = 80,
	.eccpos = {
		/* at the end of spare sector */
		48, 49, 50, 51, 52, 53, 54, 55, 56, 57,
		58, 59, 60, 61, 62, 63,	64, 65, 66, 67,
		68, 69, 70, 71, 72, 73, 74, 75, 76, 77,
		78, 79,	80, 81, 82, 83,	84, 85, 86, 87,
		88, 89, 90, 91, 92, 93,	94, 95, 96, 97,
		98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
		108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
		118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
		},
	.oobfree = {
		/* 2 bytes at offset 0 hold manufacturer badblock markers */
		{.offset = 2, .length = 46, },
		/* 5 bytes at offset 8 hold BBT markers */
		/* 8 bytes at offset 16 hold JFFS2 clean markers */
	},
};

static int __init nand_davinci_probe(struct platform_device *pdev)
{
	struct davinci_nand_pdata	*pdata = pdev->dev.platform_data;
	struct davinci_nand_info	*info;
	struct resource			*res1;
	struct resource			*res2;
	void __iomem			*vaddr;
	void __iomem			*base;
	int				ret;
	uint32_t			val;
	nand_ecc_modes_t		ecc_mode;

	/* insist on board-specific configuration */
	if (!pdata)
		return -ENODEV;

	/* which external chipselect will we be managing? */
	if (pdev->id < 0 || pdev->id > 3)
		return -ENODEV;

	info = kzalloc(sizeof(*info), GFP_KERNEL);
	if (!info) {
		dev_err(&pdev->dev, "unable to allocate memory\n");
		ret = -ENOMEM;
		goto err_nomem;
	}

	platform_set_drvdata(pdev, info);

	res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!res1 || !res2) {
		dev_err(&pdev->dev, "resource missing\n");
		ret = -EINVAL;
		goto err_nomem;
	}

	vaddr = ioremap(res1->start, resource_size(res1));
	base = ioremap(res2->start, resource_size(res2));
	if (!vaddr || !base) {
		dev_err(&pdev->dev, "ioremap failed\n");
		ret = -EINVAL;
		goto err_ioremap;
	}

	info->dev		= &pdev->dev;
	info->base		= base;
	info->vaddr		= vaddr;

	info->mtd.priv		= &info->chip;
	info->mtd.name		= dev_name(&pdev->dev);
	info->mtd.owner		= THIS_MODULE;

	info->mtd.dev.parent	= &pdev->dev;

	info->chip.IO_ADDR_R	= vaddr;
	info->chip.IO_ADDR_W	= vaddr;
	info->chip.chip_delay	= 0;
	info->chip.select_chip	= nand_davinci_select_chip;

	/* options such as NAND_USE_FLASH_BBT or 16-bit widths */
	info->chip.options	= pdata->options;
	info->chip.bbt_td	= pdata->bbt_td;
	info->chip.bbt_md	= pdata->bbt_md;
	info->timing		= pdata->timing;

	info->ioaddr		= (uint32_t __force) vaddr;

	info->current_cs	= info->ioaddr;
	info->core_chipsel	= pdev->id;
	info->mask_chipsel	= pdata->mask_chipsel;

	/* use nandboot-capable ALE/CLE masks by default */
	info->mask_ale		= pdata->mask_ale ? : MASK_ALE;
	info->mask_cle		= pdata->mask_cle ? : MASK_CLE;

	/* Set address of hardware control function */
	info->chip.cmd_ctrl	= nand_davinci_hwcontrol;
	info->chip.dev_ready	= nand_davinci_dev_ready;

	/* Speed up buffer I/O */
	info->chip.read_buf     = nand_davinci_read_buf;
	info->chip.write_buf    = nand_davinci_write_buf;

	/* Use board-specific ECC config */
	ecc_mode		= pdata->ecc_mode;

	ret = -EINVAL;
	switch (ecc_mode) {
	case NAND_ECC_NONE:
	case NAND_ECC_SOFT:
		pdata->ecc_bits = 0;
		break;
	case NAND_ECC_HW:
		if (pdata->ecc_bits == 4) {
			/* No sanity checks:  CPUs must support this,
			 * and the chips may not use NAND_BUSWIDTH_16.
			 */

			/* No sharing 4-bit hardware between chipselects yet */
			spin_lock_irq(&davinci_nand_lock);
			if (ecc4_busy)
				ret = -EBUSY;
			else
				ecc4_busy = true;
			spin_unlock_irq(&davinci_nand_lock);

			if (ret == -EBUSY)
				goto err_ecc;

			info->chip.ecc.calculate = nand_davinci_calculate_4bit;
			info->chip.ecc.correct = nand_davinci_correct_4bit;
			info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
			info->chip.ecc.bytes = 10;
		} else {
			info->chip.ecc.calculate = nand_davinci_calculate_1bit;
			info->chip.ecc.correct = nand_davinci_correct_1bit;
			info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
			info->chip.ecc.bytes = 3;
		}
		info->chip.ecc.size = 512;
		break;
	default:
		printk("RAHUL: %s @ %d Invalid ECC mode\n",__func__,__LINE__);
		ret = -EINVAL;
		goto err_ecc;
	}
	info->chip.ecc.mode = ecc_mode;

	info->clk = clk_get(&pdev->dev, "aemif");
	if (IS_ERR(info->clk)) {
		ret = PTR_ERR(info->clk);
		dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret);
		goto err_clk;
	}

	ret = clk_enable(info->clk);
	if (ret < 0) {
		dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n",
			ret);
		goto err_clk_enable;
	}

	/*
	 * Setup Async configuration register in case we did not boot from
	 * NAND and so bootloader did not bother to set it up.
	 */
	val = davinci_nand_readl(info, A1CR_OFFSET + info->core_chipsel * 4);

	/* Extended Wait is not valid and Select Strobe mode is not used */
	val &= ~(ACR_ASIZE_MASK | ACR_EW_MASK | ACR_SS_MASK);
	if (info->chip.options & NAND_BUSWIDTH_16)
		val |= 0x1;

	davinci_nand_writel(info, A1CR_OFFSET + info->core_chipsel * 4, val);

	ret = davinci_aemif_setup_timing(info->timing, info->base,
							info->core_chipsel);
	if (ret < 0) {
		dev_dbg(&pdev->dev, "NAND timing values setup fail\n");
		goto err_timing;
	}

	spin_lock_irq(&davinci_nand_lock);

	/* put CSxNAND into NAND mode */
	val = davinci_nand_readl(info, NANDFCR_OFFSET);
	val |= BIT(info->core_chipsel);
	davinci_nand_writel(info, NANDFCR_OFFSET, val);

	spin_unlock_irq(&davinci_nand_lock);

	/* Scan to find existence of the device(s) */
	ret = nand_scan_ident(&info->mtd, pdata->mask_chipsel ? 2 : 1, NULL);
	if (ret < 0) {
		dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
		goto err_scan;
	}

	/* Update ECC layout if needed ... for 1-bit HW ECC, the default
	 * is OK, but it allocates 6 bytes when only 3 are needed (for
	 * each 512 bytes).  For the 4-bit HW ECC, that default is not
	 * usable:  10 bytes are needed, not 6.
	 */
	if (pdata->ecc_bits == 4) {
		int	chunks = info->mtd.writesize / 512;

		if (!chunks || info->mtd.oobsize < 16) {
			dev_dbg(&pdev->dev, "too small\n");
			ret = -EINVAL;
			goto err_scan;
		}

		/* For small page chips, preserve the manufacturer's
		 * badblock marking data ... and make sure a flash BBT
		 * table marker fits in the free bytes.
		 */
		printk("RAHUL: %s @ %d chunks: %d\n",__func__,__LINE__,chunks);
		if (chunks == 1) {
			info->ecclayout = hwecc4_small;
			info->ecclayout.oobfree[1].length =
				info->mtd.oobsize - 16;
			goto syndrome_done;
		}
		if (chunks == 4) {
			info->ecclayout = hwecc4_2048;
			info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST;
			goto syndrome_done;
		}
		if (chunks == 8) {
			info->ecclayout = hwecc4_4096;
			info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST;
			goto syndrome_done;
		}

		/*
		 * NAND chips >4K page size are not yet supported.
		 * TODO: Note that nand_ecclayout has now been expanded and can
		 * hold plenty of OOB entries.
		 */
		dev_warn(&pdev->dev, "no 4-bit ECC support yet "
				"for >4KiB-page NAND\n");
		ret = -EIO;
		goto err_scan;

syndrome_done:
		info->chip.ecc.layout = &info->ecclayout;
	}

	ret = nand_scan_tail(&info->mtd);
	if (ret < 0)
		goto err_scan;

	if (mtd_has_partitions()) {
		struct mtd_partition	*mtd_parts = NULL;
		int			mtd_parts_nb = 0;

		if (mtd_has_cmdlinepart()) {
			static const char *probes[] __initconst =
				{ "cmdlinepart", NULL };

			mtd_parts_nb = parse_mtd_partitions(&info->mtd, probes,
							    &mtd_parts, 0);
		}

		if (mtd_parts_nb <= 0) {
			mtd_parts = pdata->parts;
			mtd_parts_nb = pdata->nr_parts;
		}

		/* Register any partitions */
		if (mtd_parts_nb > 0) {
			ret = add_mtd_partitions(&info->mtd,
					mtd_parts, mtd_parts_nb);
			if (ret == 0)
				info->partitioned = true;
		}

	} else if (pdata->nr_parts) {
		dev_warn(&pdev->dev, "ignoring %d default partitions on %s\n",
				pdata->nr_parts, info->mtd.name);
	}

	/* If there's no partition info, just package the whole chip
	 * as a single MTD device.
	 */
	if (!info->partitioned)
		ret = add_mtd_device(&info->mtd) ? -ENODEV : 0;

	if (ret < 0)
		goto err_scan;

	val = davinci_nand_readl(info, NRCSR_OFFSET);
	dev_info(&pdev->dev, "controller rev. %d.%d\n",
	       (val >> 8) & 0xff, val & 0xff);

	return 0;

err_scan:
err_timing:
	clk_disable(info->clk);

err_clk_enable:
	clk_put(info->clk);

	spin_lock_irq(&davinci_nand_lock);
	if (ecc_mode == NAND_ECC_HW_SYNDROME)
		ecc4_busy = false;
	spin_unlock_irq(&davinci_nand_lock);

err_ecc:
err_clk:
err_ioremap:
	if (base)
		iounmap(base);
	if (vaddr)
		iounmap(vaddr);

err_nomem:
	kfree(info);
	return ret;
}

static int __exit nand_davinci_remove(struct platform_device *pdev)
{
	struct davinci_nand_info *info = platform_get_drvdata(pdev);
	int status;

	if (mtd_has_partitions() && info->partitioned)
		status = del_mtd_partitions(&info->mtd);
	else
		status = del_mtd_device(&info->mtd);

	spin_lock_irq(&davinci_nand_lock);
	if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME)
		ecc4_busy = false;
	spin_unlock_irq(&davinci_nand_lock);

	iounmap(info->base);
	iounmap(info->vaddr);

	nand_release(&info->mtd);

	clk_disable(info->clk);
	clk_put(info->clk);

	kfree(info);

	return 0;
}

#ifdef CONFIG_PM
static int davinci_nand_suspend(struct platform_device *pdev,
							pm_message_t state)
{
	struct davinci_nand_info *info = platform_get_drvdata(pdev);

	clk_disable(info->clk);

	return 0;
}

static int davinci_nand_resume(struct platform_device *pdev)
{
	struct davinci_nand_info *info = platform_get_drvdata(pdev);

	clk_enable(info->clk);

	return 0;
}

#else
#define davinci_nand_suspend	NULL
#define davinci_nand_resume	NULL
#endif	/* CONFIG_PM */

static struct platform_driver nand_davinci_driver = {
	.remove		= __exit_p(nand_davinci_remove),
	.driver		= {
		.name	= "davinci_nand",
	},
	.suspend	= davinci_nand_suspend,
	.resume		= davinci_nand_resume,
};
MODULE_ALIAS("platform:davinci_nand");

static int __init nand_davinci_init(void)
{
	return platform_driver_probe(&nand_davinci_driver, nand_davinci_probe);
}
module_init(nand_davinci_init);

static void __exit nand_davinci_exit(void)
{
	platform_driver_unregister(&nand_davinci_driver);
}
module_exit(nand_davinci_exit);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("Texas Instruments");
MODULE_DESCRIPTION("Davinci NAND flash driver");

## Booting kernel from Legacy Image at c0700000 ...
   Image Name:   Linux-2.6.37+
   Image Type:   ARM Linux Kernel Image (uncompressed)
   Data Size:    2146548 Bytes = 2 MiB
   Load Address: c0008000
   Entry Point:  c0008000
   Verifying Checksum ... OK
## Loading init Ramdisk from Legacy Image at c1700000 ...
   Image Name:   uRamdisk-20140717.1309
   Image Type:   ARM Linux RAMDisk Image (gzip compressed)
   Data Size:    1744168 Bytes = 1.7 MiB
   Load Address: 00000000
   Entry Point:  00000000
   Verifying Checksum ... OK
   Loading Kernel Image ... OK
Using machid 0xca7 from environment

Starting kernel ...

Uncompressing Linux... done, booting the kernel.
Initializing cgroup subsys cpu
Linux version 2.6.37+ (rahul@rahul-c6-vm.localdomain) (gcc version 4.2.2) #25 PREEMPT Wed Jul 23 13:28:47 IST 2014
CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177
CPU: VIVT data cache, VIVT instruction cache
Machine: DaVinci DA850/OMAP-L138/AM18x EVM
Memory policy: ECC disabled, Data cache writeback
DaVinci da850/omap-l138/am18x variant 0x1
Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 65024
Kernel command line: console=ttyS2,115200n8 root=/dev/ram rw rootwait ip=off
PID hash table entries: 1024 (order: 0, 4096 bytes)
Dentry cache hash table entries: 32768 (order: 5, 131072 bytes)
Inode-cache hash table entries: 16384 (order: 4, 65536 bytes)
Memory: 256MB = 256MB total
Memory: 253628k/253628k available, 8516k reserved, 0K highmem
Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)
    DMA     : 0xff000000 - 0xffe00000   (  14 MB)
    vmalloc : 0xd0800000 - 0xfea00000   ( 738 MB)
    lowmem  : 0xc0000000 - 0xd0000000   ( 256 MB)
    modules : 0xbf000000 - 0xc0000000   (  16 MB)
      .init : 0xc0008000 - 0xc002e000   ( 152 kB)
      .text : 0xc002e000 - 0xc0421000   (4044 kB)
      .data : 0xc0422000 - 0xc044a220   ( 161 kB)
SLUB: Genslabs=13, HWalign=32, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
Preemptable hierarchical RCU implementation.
        RCU-based detection of stalled CPUs is disabled.
        Verbose stalled-CPUs detection is disabled.
NR_IRQS:245
Console: colour dummy device 80x30
Calibrating delay loop... 149.50 BogoMIPS (lpj=747520)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
DaVinci: 144 gpio irqs
regulator: core version 0.5
regulator: dummy: 
NET: Registered protocol family 16
da850_evm_init: eHRPWM module 0 cannot be used since it is being used by MII interface
bio: create slab <bio-0> at 0
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
Switching to clocksource timer0_1
musb-hdrc: version 6.0, host, debug=0
musb-hdrc musb-hdrc: dma type: dma-cppi41
Waiting for USB PHY clock good...
musb-hdrc musb-hdrc: MUSB HDRC host driver
musb-hdrc musb-hdrc: new USB bus registered, assigned bus number 1
hub 1-0:1.0: USB hub found
hub 1-0:1.0: 1 port detected
musb-hdrc musb-hdrc: USB Host mode controller at fee00000 using DMA, IRQ 58
NET: Registered protocol family 2
IP route cache hash table entries: 2048 (order: 1, 8192 bytes)
TCP established hash table entries: 8192 (order: 4, 65536 bytes)
TCP bind hash table entries: 8192 (order: 3, 32768 bytes)
TCP: Hash tables configured (established 8192 bind 8192)
TCP reno registered
UDP hash table entries: 256 (order: 0, 4096 bytes)
UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
NET: Registered protocol family 1
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module.
Trying to unpack rootfs image as initramfs...
rootfs image is not initramfs (no cpio magic); looks like an initrd
Freeing initrd memory: 1700K
EMAC: MII PHY configured, RMII PHY will not be functional
McBSP:Probed McBSP1
NTFS driver 2.1.29 [Flags: R/O].
JFFS2 version 2.2. (NAND) �© 2001-2006 Red Hat, Inc.
msgmni has been set to 498
io scheduler noop registered
io scheduler deadline registered
io scheduler cfq registered (default)
Serial: 8250/16550 driver, 3 ports, IRQ sharing disabled
serial8250.0: ttyS0 at MMIO 0x1c42000 (irq = 25) is a AR7
serial8250.0: ttyS1 at MMIO 0x1d0c000 (irq = 53) is a AR7
serial8250.0: ttyS2 at MMIO 0x1d0d000 (irq = 61) is a AR7
console [ttyS2] enabled
brd: module loaded
ahci ahci: forcing PORTS_IMPL to 0x1
ahci ahci: AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl platform mode
ahci ahci: flags: ncq sntf pm led clo only pmp pio slum part ccc 
scsi0 : ahci_platform
ata1: SATA max UDMA/133 mmio [mem 0x01e18000-0x01e19fff] port 0x100 irq 67
davinci-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank. Manufacturer ID 0x000001 Chip ID 0x002201
Amd/Fujitsu Extended Query Table at 0x0040
  Amd/Fujitsu Extended Query version 1.3.
number of CFI chips: 1
Creating 7 MTD partitions on "davinci-flash.0":
0x000000000000-0x000000020000 : "UBL"
0x000000020000-0x000000080000 : "U-Boot"
0x000000080000-0x0000000a0000 : "U-Boot-Env"
0x0000000a0000-0x0000003a0000 : "Kernel"
0x0000003a0000-0x0000017a0000 : "Filesystem"
0x000001fa0000-0x000001fc0000 : "System"
0x000001fe0000-0x000002000000 : "MAC-Address"
Read MAC addr from NOR Flash: 00:aa:bb:cc:dd:72
ONFI flash detected
ONFI param page 0 valid
RAHUL: nand_flash_detect_onfi @ 2862 NAND_TIMING_MODE: [1f]
NAND device: Manufacturer ID: 0x2c, Chip ID: 0x48 (Micron (null))
2 NAND chips detected
RAHUL: nand_davinci_probe @ 753 chunks: 8
Creating 2 MTD partitions on "davinci_nand.1":
0x000000000000-0x000080000000 : "NANDP1"
0x000080000000-0x000100000000 : "NandFS"
davinci_nand davinci_nand.1: controller rev. 2.5
davinci_mdio davinci_mdio.0: davinci mdio revision 1.5
davinci_mdio davinci_mdio.0: detected phy mask e0000fd8
davinci_mdio.0: probed
davinci_mdio davinci_mdio.0: phy[0]: device 0:00, driver Marvell 88E1121R
davinci_mdio davinci_mdio.0: phy[1]: device 0:01, driver Marvell 88E1121R
davinci_mdio davinci_mdio.0: phy[2]: device 0:02, driver Marvell 88E1121R
davinci_mdio davinci_mdio.0: phy[5]: device 0:05, driver Marvell 88E1112
console [netcon0] enabled
netconsole: network logging started
ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
ohci ohci.0: DA8xx OHCI
ohci ohci.0: new USB bus registered, assigned bus number 2
ata1: SATA link down (SStatus 0 SControl 300)
Waiting for USB PHY clock good...
ohci ohci.0: irq 59, io mem 0x01e25000
hub 2-0:1.0: USB hub found
hub 2-0:1.0: 1 port detected
Initializing USB Mass Storage driver...
usbcore: registered new interface driver usb-storage
USB Mass Storage support registered.
omap_rtc omap_rtc: rtc core: registered omap_rtc as rtc0
omap_rtc: RTC power up reset detected
omap_rtc: already running
watchdog watchdog: heartbeat 60 sec
cpuidle: using governor ladder
cpuidle: using governor menu
TCP cubic registered
NET: Registered protocol family 10
NET: Registered protocol family 17
deviceless supply cvdd not found, using dummy regulator
davinci_emac_probe: using random MAC addr: fe:3e:ab:d6:e0:1e
Distributed Switch Architecture driver version 0.1
cpu[0]: detected a Marvell 88E6122 switch
dsa slave smi: probed
dsa_slave_create:serdes DSA using random MAC addr: fe:86:df:21:c3:e0
omap_rtc omap_rtc: setting system clock to 2014-07-23 13:30:40 UTC (1406122240)
RAMDISK: gzip image found at block 0
VFS: Mounted root (ext2 filesystem) on device 1:0.
Freeing init memory: 152K
Starting mdev...
Starting logging: OK
hub 2-0:1.0: Cannot enable port 1.  Maybe the USB cable is bad?
Initializing random number generator... done.
Starting network...

Welcome to cpuIP
cpuIP login: hub 2-0:1.0: Cannot enable port 1.  Maybe the USB cable is bad?
hub 2-0:1.0: Cannot enable port 1.  Maybe the USB cable is bad?
hub 2-0:1.0: Cannot enable port 1.  Maybe the USB cable is bad?
hub 2-0:1.0: unable to enumerate USB device on port 1

Welcome to cpuIP
cpuIP login: root
Password: 
# 
# tail -100 /var/log/messages 
Jul 23 13:30:42 cpuIP kern.info kernel: UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
Jul 23 13:30:42 cpuIP kern.info kernel: NET: Registered protocol family 1
Jul 23 13:30:42 cpuIP kern.info kernel: RPC: Registered udp transport module.
Jul 23 13:30:42 cpuIP kern.info kernel: RPC: Registered tcp transport module.
Jul 23 13:30:42 cpuIP kern.info kernel: RPC: Registered tcp NFSv4.1 backchannel transport module.
Jul 23 13:30:42 cpuIP kern.info kernel: Trying to unpack rootfs image as initramfs...
Jul 23 13:30:42 cpuIP kern.info kernel: rootfs image is not initramfs (no cpio magic); looks like an initrd
Jul 23 13:30:42 cpuIP kern.info kernel: Freeing initrd memory: 1700K
Jul 23 13:30:42 cpuIP kern.info kernel: EMAC: MII PHY configured, RMII PHY will not be functional
Jul 23 13:30:42 cpuIP kern.info kernel: McBSP:Probed McBSP1
Jul 23 13:30:42 cpuIP kern.info kernel: NTFS driver 2.1.29 [Flags: R/O].
Jul 23 13:30:42 cpuIP kern.info kernel: JFFS2 version 2.2. (NAND) �© 2001-2006 Red Hat, Inc.
Jul 23 13:30:42 cpuIP kern.info kernel: msgmni has been set to 498
Jul 23 13:30:42 cpuIP kern.info kernel: io scheduler noop registered
Jul 23 13:30:42 cpuIP kern.info kernel: io scheduler deadline registered
Jul 23 13:30:42 cpuIP kern.info kernel: io scheduler cfq registered (default)
Jul 23 13:30:42 cpuIP kern.info kernel: Serial: 8250/16550 driver, 3 ports, IRQ sharing disabled
Jul 23 13:30:42 cpuIP kern.info kernel: serial8250.0: ttyS0 at MMIO 0x1c42000 (irq = 25) is a AR7
Jul 23 13:30:42 cpuIP kern.info kernel: serial8250.0: ttyS1 at MMIO 0x1d0c000 (irq = 53) is a AR7
Jul 23 13:30:42 cpuIP kern.info kernel: serial8250.0: ttyS2 at MMIO 0x1d0d000 (irq = 61) is a AR7
Jul 23 13:30:42 cpuIP kern.info kernel: console [ttyS2] enabled
Jul 23 13:30:42 cpuIP kern.info kernel: brd: module loaded
Jul 23 13:30:42 cpuIP kern.warn kernel: ahci ahci: forcing PORTS_IMPL to 0x1
Jul 23 13:30:42 cpuIP kern.info kernel: ahci ahci: AHCI 0001.0100 32 slots 1 ports 3 Gbps 0x1 impl platform mode
Jul 23 13:30:42 cpuIP kern.info kernel: ahci ahci: flags: ncq sntf pm led clo only pmp pio slum part ccc 
Jul 23 13:30:42 cpuIP kern.info kernel: scsi0 : ahci_platform
Jul 23 13:30:42 cpuIP kern.info kernel: ata1: SATA max UDMA/133 mmio [mem 0x01e18000-0x01e19fff] port 0x100 irq 67
Jul 23 13:30:42 cpuIP kern.info kernel: davinci-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank. Manufacturer ID 0x000001 Chip ID 0x002201
Jul 23 13:30:42 cpuIP kern.info kernel: Amd/Fujitsu Extended Query Table at 0x0040
Jul 23 13:30:42 cpuIP kern.info kernel:   Amd/Fujitsu Extended Query version 1.3.
Jul 23 13:30:42 cpuIP kern.notice kernel: number of CFI chips: 1
Jul 23 13:30:42 cpuIP kern.notice kernel: Creating 7 MTD partitions on "davinci-flash.0":
Jul 23 13:30:42 cpuIP kern.notice kernel: 0x000000000000-0x000000020000 : "UBL"
Jul 23 13:30:42 cpuIP kern.notice kernel: 0x000000020000-0x000000080000 : "U-Boot"
Jul 23 13:30:42 cpuIP kern.notice kernel: 0x000000080000-0x0000000a0000 : "U-Boot-Env"
Jul 23 13:30:42 cpuIP kern.notice kernel: 0x0000000a0000-0x0000003a0000 : "Kernel"
Jul 23 13:30:42 cpuIP kern.notice kernel: 0x0000003a0000-0x0000017a0000 : "Filesystem"
Jul 23 13:30:42 cpuIP kern.notice kernel: 0x000001fa0000-0x000001fc0000 : "System"
Jul 23 13:30:42 cpuIP kern.notice kernel: 0x000001fe0000-0x000002000000 : "MAC-Address"
Jul 23 13:30:42 cpuIP kern.info kernel: Read MAC addr from NOR Flash: 00:aa:bb:cc:dd:72
Jul 23 13:30:42 cpuIP kern.info kernel: ONFI flash detected
Jul 23 13:30:42 cpuIP kern.info kernel: ONFI param page 0 valid
Jul 23 13:30:42 cpuIP kern.warn kernel: RAHUL: nand_flash_detect_onfi @ 2862 NAND_TIMING_MODE: [1f]
Jul 23 13:30:42 cpuIP kern.info kernel: NAND device: Manufacturer ID: 0x2c, Chip ID: 0x48 (Micron (null))
Jul 23 13:30:42 cpuIP kern.info kernel: 2 NAND chips detected
Jul 23 13:30:42 cpuIP kern.warn kernel: RAHUL: nand_davinci_probe @ 753 chunks: 8
Jul 23 13:30:42 cpuIP kern.debug kernel: Bad block table found at page 524160, version 0x01
Jul 23 13:30:42 cpuIP kern.debug kernel: Bad block table found at page 1048448, version 0x01
Jul 23 13:30:42 cpuIP kern.debug kernel: Bad block table found at page 524032, version 0x01
Jul 23 13:30:42 cpuIP kern.debug kernel: Bad block table found at page 1048320, version 0x01
Jul 23 13:30:42 cpuIP kern.notice kernel: Creating 2 MTD partitions on "davinci_nand.1":
Jul 23 13:30:42 cpuIP kern.notice kernel: 0x000000000000-0x000080000000 : "NANDP1"
Jul 23 13:30:42 cpuIP kern.notice kernel: 0x000080000000-0x000100000000 : "NandFS"
Jul 23 13:30:42 cpuIP kern.info kernel: davinci_nand davinci_nand.1: controller rev. 2.5
Jul 23 13:30:42 cpuIP kern.info kernel: davinci_mdio davinci_mdio.0: davinci mdio revision 1.5
Jul 23 13:30:42 cpuIP kern.info kernel: davinci_mdio davinci_mdio.0: detected phy mask e0000fd8
Jul 23 13:30:42 cpuIP kern.info kernel: davinci_mdio.0: probed
Jul 23 13:30:42 cpuIP kern.info kernel: davinci_mdio davinci_mdio.0: phy[0]: device 0:00, driver Marvell 88E1121R
Jul 23 13:30:42 cpuIP kern.info kernel: davinci_mdio davinci_mdio.0: phy[1]: device 0:01, driver Marvell 88E1121R
Jul 23 13:30:42 cpuIP kern.info kernel: davinci_mdio davinci_mdio.0: phy[2]: device 0:02, driver Marvell 88E1121R
Jul 23 13:30:42 cpuIP kern.info kernel: davinci_mdio davinci_mdio.0: phy[5]: device 0:05, driver Marvell 88E1112
Jul 23 13:30:42 cpuIP kern.info kernel: console [netcon0] enabled
Jul 23 13:30:42 cpuIP kern.info kernel: netconsole: network logging started
Jul 23 13:30:42 cpuIP kern.info kernel: ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
Jul 23 13:30:42 cpuIP kern.info kernel: ohci ohci.0: DA8xx OHCI
Jul 23 13:30:42 cpuIP kern.info kernel: ohci ohci.0: new USB bus registered, assigned bus number 2
Jul 23 13:30:42 cpuIP kern.info kernel: ata1: SATA link down (SStatus 0 SControl 300)
Jul 23 13:30:42 cpuIP kern.info kernel: Waiting for USB PHY clock good...
Jul 23 13:30:42 cpuIP kern.info kernel: ohci ohci.0: irq 59, io mem 0x01e25000
Jul 23 13:30:42 cpuIP kern.info kernel: hub 2-0:1.0: USB hub found
Jul 23 13:30:42 cpuIP kern.info kernel: hub 2-0:1.0: 1 port detected
Jul 23 13:30:42 cpuIP kern.info kernel: Initializing USB Mass Storage driver...
Jul 23 13:30:42 cpuIP kern.info kernel: usbcore: registered new interface driver usb-storage
Jul 23 13:30:42 cpuIP kern.info kernel: USB Mass Storage support registered.
Jul 23 13:30:42 cpuIP kern.info kernel: omap_rtc omap_rtc: rtc core: registered omap_rtc as rtc0
Jul 23 13:30:42 cpuIP kern.info kernel: omap_rtc: RTC power up reset detected
Jul 23 13:30:42 cpuIP kern.info kernel: omap_rtc: already running
Jul 23 13:30:42 cpuIP kern.info kernel: watchdog watchdog: heartbeat 60 sec
Jul 23 13:30:42 cpuIP kern.info kernel: cpuidle: using governor ladder
Jul 23 13:30:42 cpuIP kern.info kernel: cpuidle: using governor menu
Jul 23 13:30:42 cpuIP kern.info kernel: TCP cubic registered
Jul 23 13:30:42 cpuIP kern.info kernel: NET: Registered protocol family 10
Jul 23 13:30:42 cpuIP kern.info kernel: NET: Registered protocol family 17
Jul 23 13:30:42 cpuIP kern.warn kernel: deviceless supply cvdd not found, using dummy regulator
Jul 23 13:30:42 cpuIP kern.warn kernel: davinci_emac_probe: using random MAC addr: fe:3e:ab:d6:e0:1e
Jul 23 13:30:42 cpuIP kern.notice kernel: Distributed Switch Architecture driver version 0.1
Jul 23 13:30:42 cpuIP kern.info kernel: cpu[0]: detected a Marvell 88E6122 switch
Jul 23 13:30:42 cpuIP kern.info kernel: dsa slave smi: probed
Jul 23 13:30:42 cpuIP kern.warn kernel: dsa_slave_create:serdes DSA using random MAC addr: fe:86:df:21:c3:e0
Jul 23 13:30:42 cpuIP kern.info kernel: omap_rtc omap_rtc: setting system clock to 2014-07-23 13:30:40 UTC (1406122240)
Jul 23 13:30:42 cpuIP kern.notice kernel: RAMDISK: gzip image found at block 0
Jul 23 13:30:42 cpuIP kern.warn kernel: VFS: Mounted root (ext2 filesystem) on device 1:0.
Jul 23 13:30:42 cpuIP kern.info kernel: Freeing init memory: 152K
Jul 23 13:30:42 cpuIP kern.err kernel: hub 2-0:1.0: Cannot enable port 1.  Maybe the USB cable is bad?
Jul 23 13:30:43 cpuIP daemon.info init: starting pid 607, tty '/dev/ttyS2': '/sbin/getty -L ttyS2 115200 vt100 '
Jul 23 13:30:45 cpuIP kern.err kernel: hub 2-0:1.0: Cannot enable port 1.  Maybe the USB cable is bad?
Jul 23 13:30:48 cpuIP kern.err kernel: hub 2-0:1.0: Cannot enable port 1.  Maybe the USB cable is bad?
Jul 23 13:30:52 cpuIP kern.err kernel: hub 2-0:1.0: Cannot enable port 1.  Maybe the USB cable is bad?
Jul 23 13:30:52 cpuIP kern.err kernel: hub 2-0:1.0: unable to enumerate USB device on port 1
Jul 23 13:31:27 cpuIP auth.info login[607]: root login on 'ttyS2'
# 
# mount -t jffs2 /dev/mtdblock7 /opt/
Cowardly refusing to erase blocks on filesystem with no valid JFFS2 nodes
empty_blocks 1984, bad_blocks 4, c->nr_blocks 4096
mount: mounting /dev/mtdblock7 on /opt/ failed: Input/output error
# 
# mount -t jffs2 /dev/mtdblock8 /mnt/
# 
# tail -20 /var/log/messages 
Jul 23 13:30:42 cpuIP kern.info kernel: NET: Registered protocol family 17
Jul 23 13:30:42 cpuIP kern.warn kernel: deviceless supply cvdd not found, using dummy regulator
Jul 23 13:30:42 cpuIP kern.warn kernel: davinci_emac_probe: using random MAC addr: fe:3e:ab:d6:e0:1e
Jul 23 13:30:42 cpuIP kern.notice kernel: Distributed Switch Architecture driver version 0.1
Jul 23 13:30:42 cpuIP kern.info kernel: cpu[0]: detected a Marvell 88E6122 switch
Jul 23 13:30:42 cpuIP kern.info kernel: dsa slave smi: probed
Jul 23 13:30:42 cpuIP kern.warn kernel: dsa_slave_create:serdes DSA using random MAC addr: fe:86:df:21:c3:e0
Jul 23 13:30:42 cpuIP kern.info kernel: omap_rtc omap_rtc: setting system clock to 2014-07-23 13:30:40 UTC (1406122240)
Jul 23 13:30:42 cpuIP kern.notice kernel: RAMDISK: gzip image found at block 0
Jul 23 13:30:42 cpuIP kern.warn kernel: VFS: Mounted root (ext2 filesystem) on device 1:0.
Jul 23 13:30:42 cpuIP kern.info kernel: Freeing init memory: 152K
Jul 23 13:30:42 cpuIP kern.err kernel: hub 2-0:1.0: Cannot enable port 1.  Maybe the USB cable is bad?
Jul 23 13:30:43 cpuIP daemon.info init: starting pid 607, tty '/dev/ttyS2': '/sbin/getty -L ttyS2 115200 vt100 '
Jul 23 13:30:45 cpuIP kern.err kernel: hub 2-0:1.0: Cannot enable port 1.  Maybe the USB cable is bad?
Jul 23 13:30:48 cpuIP kern.err kernel: hub 2-0:1.0: Cannot enable port 1.  Maybe the USB cable is bad?
Jul 23 13:30:52 cpuIP kern.err kernel: hub 2-0:1.0: Cannot enable port 1.  Maybe the USB cable is bad?
Jul 23 13:30:52 cpuIP kern.err kernel: hub 2-0:1.0: unable to enumerate USB device on port 1
Jul 23 13:31:27 cpuIP auth.info login[607]: root login on 'ttyS2'
Jul 23 15:03:36 cpuIP kern.notice kernel: Cowardly refusing to erase blocks on filesystem with no valid JFFS2 nodes
Jul 23 15:03:36 cpuIP kern.notice kernel: empty_blocks 1984, bad_blocks 4, c->nr_blocks 4096
# 
# 
# mkdir /mnt/rahul
# 
# tail -20 /var/log/messages 
Jul 23 13:30:42 cpuIP kern.info kernel: NET: Registered protocol family 17
Jul 23 13:30:42 cpuIP kern.warn kernel: deviceless supply cvdd not found, using dummy regulator
Jul 23 13:30:42 cpuIP kern.warn kernel: davinci_emac_probe: using random MAC addr: fe:3e:ab:d6:e0:1e
Jul 23 13:30:42 cpuIP kern.notice kernel: Distributed Switch Architecture driver version 0.1
Jul 23 13:30:42 cpuIP kern.info kernel: cpu[0]: detected a Marvell 88E6122 switch
Jul 23 13:30:42 cpuIP kern.info kernel: dsa slave smi: probed
Jul 23 13:30:42 cpuIP kern.warn kernel: dsa_slave_create:serdes DSA using random MAC addr: fe:86:df:21:c3:e0
Jul 23 13:30:42 cpuIP kern.info kernel: omap_rtc omap_rtc: setting system clock to 2014-07-23 13:30:40 UTC (1406122240)
Jul 23 13:30:42 cpuIP kern.notice kernel: RAMDISK: gzip image found at block 0
Jul 23 13:30:42 cpuIP kern.warn kernel: VFS: Mounted root (ext2 filesystem) on device 1:0.
Jul 23 13:30:42 cpuIP kern.info kernel: Freeing init memory: 152K
Jul 23 13:30:42 cpuIP kern.err kernel: hub 2-0:1.0: Cannot enable port 1.  Maybe the USB cable is bad?
Jul 23 13:30:43 cpuIP daemon.info init: starting pid 607, tty '/dev/ttyS2': '/sbin/getty -L ttyS2 115200 vt100 '
Jul 23 13:30:45 cpuIP kern.err kernel: hub 2-0:1.0: Cannot enable port 1.  Maybe the USB cable is bad?
Jul 23 13:30:48 cpuIP kern.err kernel: hub 2-0:1.0: Cannot enable port 1.  Maybe the USB cable is bad?
Jul 23 13:30:52 cpuIP kern.err kernel: hub 2-0:1.0: Cannot enable port 1.  Maybe the USB cable is bad?
Jul 23 13:30:52 cpuIP kern.err kernel: hub 2-0:1.0: unable to enumerate USB device on port 1
Jul 23 13:31:27 cpuIP auth.info login[607]: root login on 'ttyS2'
Jul 23 15:03:36 cpuIP kern.notice kernel: Cowardly refusing to erase blocks on filesystem with no valid JFFS2 nodes
Jul 23 15:03:36 cpuIP kern.notice kernel: empty_blocks 1984, bad_blocks 4, c->nr_blocks 4096
# 
# umount /mnt/
# tail -20 /var/log/messages 
Jul 23 13:30:42 cpuIP kern.info kernel: NET: Registered protocol family 17
Jul 23 13:30:42 cpuIP kern.warn kernel: deviceless supply cvdd not found, using dummy regulator
Jul 23 13:30:42 cpuIP kern.warn kernel: davinci_emac_probe: using random MAC addr: fe:3e:ab:d6:e0:1e
Jul 23 13ted a Marvell 88E6122 switch
Jul 23 13:30:42 cpuIP kern.info kernel: dsa slave smi: probed
Jul 23 13:30:42 cpuIP kern.warn kernel: dsa_slave_create:serdes DSA using random MAC addr: fe:86:df:21:c3:e0
Jul 23 13:30:42 cpuIP kern.info kernel: omap_rtc omap_rtc: setting system clock to 2014-07-23 13:30:40 UTC (1406122240)
Jul 23 13:30:42 cpuIP kern.notice kernel: RAMDISK: gzip image found at block 0
Jul 23 13:30:42 cpuIP kern.warn kernel: VFS: Mounted root (ext2 filesystem) on device 1:0.
Jul 23 13:30:42 cpuIP kern.info kernel: Freeing init memory: 152K
Jul 23 13:30:42 cpuIP kern.err kernel: hub 2-0:1.0: Cannot enable port 1.  Maybe the USB cable is bad?
Jul 23 13:30:43 cpuIP daemon.info init: starting pid 607, tty '/dev/ttyS2': '/sbin/getty -L ttyS2 115200 vt100 '
Jul 23 13:30:45 cpuIP kern.err kernel: hub 2-0:1.0: Cannot enable port 1.  Maybe the USB cable is bad?
Jul 23 13:30:48 cpuIP kern.err kernel: hub 2-0:1.0: Cannot enable port 1.  Maybe the USB cable is bad?
Jul 23 13:30:52 cpuIP kern.err kernel: hub 2-0:1.0: Cannot enable port 1.  Maybe the USB cable is bad?
Jul 23 13:30:52 cpuIP kern.err kernel: hub 2-0:1.0: unable to enumerate USB device on port 1
Jul 23 13:31:27 cpuIP auth.info login[607]: root login on 'ttyS2'
Jul 23 15:03:36 cpuIP kern.notice kernel: Cowardly refusing to erase blocks on filesystem with no valid JFFS2 nodes
Jul 23 15:03:36 cpuIP kern.notice kernel: empty_blocks 1984, bad_blocks 4, c->nr_blocks 4096
# 
# 
# mount -t jffs2 /dev/mtdblock8 /mnt/
# ls /mnt/