Hi,
I am using McASP port in OMAPL138 to transmit 24-bit data to 2 DACs (PCM1753) on AXR8 and AXR15. I am using CCS Version: 5.4.0.00091, and it is NON-OS development.
I have made changes to McASP example in “quickStartOMAPL1x_rCSL” library, to just use Tx section and generate Tx clocks for our custom board. I have programmed these clocks for our requirement, cpu clock=375 MHz, McASP clock = 187.5 MHz.and DAC fs=192k.
I am trying to look at these signals on an oscilloscope. I see all the clocks (ACLKX, AHCLKX and AFSX) fine. I am generating McASP event interrupt fine (XDATA enabled). I see the data in AXR8 and AXR15 buffers. But I don’t see the data in oscilloscope. I have tested those pins for any hardware issues by configuring them as GPIOs and sending data on them and they work fine.
I am using TDM transfer mode.
Here are the changes I made in the initialization.
/*Transmit Format Unit */
//For I2S, MSB First, Left aligned, XATDLY=1
CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XDATDLY, 1BIT);
CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XRVRS, MSBFIRST);
CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XPAD, ZERO);
//CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XSSZ, 32BITS);
CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XSSZ, 24BITS);
CSL_FINS(mcaspRegs->XFMT, MCASP_XFMT_XPBIT, 0);
CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XROT, NONE);
CSL_FINST(mcaspRegs->XFMT, MCASP_XFMT_XBUSEL, VBUS);
/*Transmit Frame Sync Control Register */
//Frame Sync is configured for I2S (2-slot TDM (I2S mode) to 32-slot TDM)
CSL_FINST(mcaspRegs->AFSXCTL, MCASP_AFSXCTL_XMOD, I2S); //=2
//Frame Sync Length is Word (=1)
CSL_FINST(mcaspRegs->AFSXCTL, MCASP_AFSXCTL_FXWID, WORD);
//Transmit frame sync generation select bit.
//Frame Sync is internally generated by XCLK (=1)
CSL_FINST(mcaspRegs->AFSXCTL, MCASP_AFSXCTL_FSXM, INTERNAL);
//Transmit frame sync polarity select bit.
//Falling Edge indicates beginning of new word (=1)
CSL_FINST(mcaspRegs->AFSXCTL, MCASP_AFSXCTL_FSXP, FALLINGEDGE);
//Active Slots 0/1 for I2S
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS1, ACTIVE);
CSL_FINST(mcaspRegs->XTDM, MCASP_XTDM_XTDMS0, ACTIVE);
CSL_FINST(mcaspRegs->XINTCTL, MCASP_XINTCTL_XDATA, ENABLE);
//Configure Serializer 8, 15 to be Transmit Serializers
CSL_FINST(mcaspRegs->SRCTL8, MCASP_SRCTL8_SRMOD, XMT);
CSL_FINST(mcaspRegs->SRCTL15, MCASP_SRCTL15_SRMOD, XMT);
//Configure AHCLKX, ACLKX, AFSX, AXR11, AXR12 as McASP Pins vs. GPIO Pins
CSL_FINST(mcaspRegs->PFUNC, MCASP_PFUNC_AFSX, MCASP);
CSL_FINST(mcaspRegs->PFUNC, MCASP_PFUNC_AHCLKX, MCASP);
CSL_FINST(mcaspRegs->PFUNC, MCASP_PFUNC_ACLKX, MCASP);
CSL_FINST(mcaspRegs->PFUNC, MCASP_PFUNC_AXR8, MCASP);
CSL_FINST(mcaspRegs->PFUNC, MCASP_PFUNC_AXR15, MCASP);
//Configure the AHCLKX, ACLKX, AFSX, AXR11 as Output Pins to send
CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AFSX, OUTPUT);
CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AHCLKX, OUTPUT);
CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_ACLKX, OUTPUT);
CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AXR15, OUTPUT);
CSL_FINST(mcaspRegs->PDIR, MCASP_PDIR_AXR8, OUTPUT);
Rest of the initialization, mcasp_start and ISR are same as in the example.
It would be of great help if someone can advise me. I should be able to see data on these pins on oscilloscope. Am I missing anything in configuration?
Also, if I send data on both pins, I get only 2 interrupts. How do I configure TDM slots to send data on both the pins every time I interrupt?
Many thanks in advance,
Prathibha