Problems with MCasP on Omap L-138

marek Natunewicz

Other Parts Discussed in Thread: OMAPL138

Hello

I have some problem with running McaSP module in Burst Mode. I need this module to send dat in to dac Converter.

After init procedure when I try send data writes bytes in to XBUF register using AXR8 pins every 2 seconds. After that I can't see anything on output.

Here is my init Procedure:

HWREG(SOC_MCASP_0_CTRL_REGS + MCASP_XMASK) = 0xFF;
HWREG(SOC_MCASP_0_CTRL_REGS + MCASP_XFMT) =(1<<15);//msb first
HWREG(SOC_MCASP_0_CTRL_REGS + MCASP_XFMT) |=(0xf<<4); //slot size 32 bits
HWREG(SOC_MCASP_0_CTRL_REGS + MCASP_XFMT) =(1<<3); //ignore dma

HWREG(SOC_MCASP_0_CTRL_REGS + MCASP_AFSXCTL) =0; //turn off sync control register

HWREG(SOC_MCASP_0_CTRL_REGS + MCASP_ACLKXCTL) =(1<<5); //internal clock
HWREG(SOC_MCASP_0_CTRL_REGS + MCASP_ACLKXCTL) |=32; //clock divider on 32
HWREG(SOC_MCASP_0_CTRL_REGS + MCASP_ACLKXCTL) |=(1<<7);

HWREG(SOC_MCASP_0_CTRL_REGS + MCASP_AHCLKXCTL) =(1<<15); //internal closk
HWREG(SOC_MCASP_0_CTRL_REGS + MCASP_AHCLKXCTL) |=100;//divider

HWREG(SOC_MCASP_0_CTRL_REGS + MCASP_XTDM) = 1; //one slot active

HWREG(SOC_MCASP_0_CTRL_REGS + MCASP_XINTCTL) = 0; //turn off interrupt

HWREG(SOC_MCASP_0_CTRL_REGS + MCASP_XCLKCHK) = 6; //divide 64

HWREG(SOC_MCASP_0_CTRL_REGS + MCASP_PFUNC) = 0xFC00; //usawienie pinow dunkcjonalnych dal modulu AXR, i pozostalych
HWREG(SOC_MCASP_0_CTRL_REGS + MCASP_PDIR) = 0xFE0003FF; //istawienie kierunku pracy dla pinow...

HWREG(SOC_MCASP_0_CTRL_REGS + MCASP_SRCTL(8)) = 1; //ustawienie serializatorow jako transmisja

HWREG(SOC_MCASP_0_CTRL_REGS + MCASP_GBLCTL) = (1<<9);

while(((SOC_MCASP_0_CTRL_REGS + MCASP_GBLCTL) & (1<<9)))
;

HWREG(SOC_MCASP_0_CTRL_REGS + MCASP_GBLCTL) = (1<<8);

while(((SOC_MCASP_0_CTRL_REGS + MCASP_GBLCTL) & (1<<8)))
;

HWREG(SOC_MCASP_0_CTRL_REGS + MCASP_XSTAT) = 0x0000FFFF; //wyczyszczenie rejestru zwiazanego z statusem od nadajnika

HWREG(SOC_MCASP_0_CTRL_REGS + MCASP_GBLCTL) = (1<<10);

while(((SOC_MCASP_0_CTRL_REGS + MCASP_GBLCTL) & (1<<10)))
;

HWREG(SOC_MCASP_0_CTRL_REGS + MCASP_XBUF(8)) =0x55555555;

HWREG(SOC_MCASP_0_CTRL_REGS + MCASP_GBLCTL) = (1<<11);
while(((SOC_MCASP_0_CTRL_REGS + MCASP_GBLCTL) & (1<<11)))
;
Please help me to find where is the problems
Marek

over 9 years ago

0 Sivaraj Kuppuraj over 9 years ago

TI__Mastermind 35645 points

Hi,

Thanks for your post.

Have you tried probing the data on AXR8 pin on the scope to see what's messing up there? You could tap the data of XBUF data register through AXR8 and you could also check the McASP's bit clock (ACLKX), Tx. frame sync (AFSX), high frequency clock (AHCLKX) and probe the data at corresponding pins. Please give us more info. on this.

Could you please give us the McASP register dump to investigate more and to evaluate the cause of the issue?

Thanks & regards,

Sivaraj K

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0 marek Natunewicz over 9 years ago in reply to Sivaraj Kuppuraj

Prodigy 20 points

Hello Sivaraj

I probed AXR8 and ACLKX pins using scope. On the ACLK I saw the correct clock signal, but on the AXR8 I didn’t see anything. Example sending procedure look like this:

HWREG(SOC_MCASP_0_CTRL_REGS + MCASP_XBUF(8)) =0x55555555;

I try send test data every 2 second in main loop. I try run this program on omap L138 on ARM side. The clock processor is set to 375MHz.

The MCasp dump register:

Thanks & regards,

Marek

0 Sivaraj Kuppuraj over 9 years ago in reply to marek Natunewicz

TI__Mastermind 35645 points

Hi,

Your McASP register dump configuration seems to be ok.

I think, the input audio would be fed to the McASP's AXR13 and the output audio would be sourced from McASP's AXR14. The codec BCLK is connected to the McASP ACLKX pin, and the WCLK is connected to the McASP AFSX pin.

Are you using TI's OMAPL138 EVM or LCDK board or is it any custom or third party board? If TI board, please refer the omapl138 schematics to which transmit serializers and receiver serializers are mapped and you could tap the data to the corresponding serializers mapped & probe the data through the scope.

Also check the AIC3106 codec's BCLK & WCLK pins too, whether the audio output data reside in the corresponding output AXR's should send an interrupt to DAC to receive data from McASP's output serializer. Kindly ensure the output data available to DAC's corresponding pins and you could probe the data on the DAC side too, so that, you could tap the data thorugh LINEOUT. Please debug the code step by step, whether the McASP sends the interrupt to DAC to signal the DAC to receive data from McASP's output serializers and DAC codec registers should be configured appropriately to receive data from McASP, so that, you will have output audio through LINE OUT port.

I think, we could debug the code step by step and check whether McASP is hitting the interrupt to DAC, whether the output audio data available to both McASP & DAC. Also, check the below wiki's:

http://processors.wiki.ti.com/index.php/McASP_Tips

http://processors.wiki.ti.com/index.php/StarterWare_01.10.01.01_User_Guide#Example_Application_9

http://processors.wiki.ti.com/index.php/StarterWare_Audio_Application

Thanks & regards,

Sivaraj K

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