Hi All,
Have a great day.
Subject: Transfer parallel data from AM1808 to customer board with WAIT activated.
Board Setup: AM1808 board interfaced with customer board (receiver chip).
The setup is AM1808 will send 8 bit parallel data on channel-B (transmit mode) along with CLOCK (output) and ENABLE (output) which act as DATA-VALID. The receiver chip will capture data when ENABLE=1. This setup works fine as expected. i.e. The data transfer from AM1808 to receiver chip is successful.
Now the receiver chip want's to halt the transfer (if its internal FIFO goes to almost full) so we have configured WAIT (input to AM1808) signal with ACTIVE high polarity. Here are the more register setting for uPP interface.
UPICR.TRISB=0
UPICR.WAITB=1 (WAIT is enabled for channel-B)
UPICR.WAITPOLB=0 (WAIT is configured as active HIGH)
UPCTL.MODE[1:0] [Field 1to 0] = 1h (All transmit mode)
The issue we noticed is AM1808 is continue sending DATA even though WAIT is set to logical HIGH. The expected behavior is AM1808 should stop sending data. Also observed that WAIT signal is forcefully driven to active LOW by AM1808 even though we configured as INPUT mode.
Please help us to solve above issue, I am ready to share more details if required. Thanks a lot.
Best Regards,
Magesh S