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Can I use async EMIF space synchronously?

John Johnson3
Prodigy 100 points

Using a 6748, with EMIF CS3 to access my FPGA's register bank

It appears CS0 is intended for synchronous use with SDRAM, while CS[2:5] are intended for interfacing to async devices.

But from first looks at the data sheet timing, it appears I could use the EMA_CLK as a clock to my FPGA (selected by CS3) and treat it as a fully synchronous interface (like a clocked SRAM).

Is there any reason I couldn't do this?

The async interface options are to either sample the EMIF Addr, Data, OE, WE, etc... on my FPGA core clock (no relation to EMIF clock), and include the appropriate metastability-minimizing synchronization registers, or use the edges of OE and WE as clocks at that interface.

I realize all 3 approaches require metastability-handling registers when crossing over into my FPGA core clock domain; don't worry, they will be there. :)

I just prefer first approach (all synchronous) if possible, where the boundary crossings can happen in something like a FIFO that doesn't generate a bunch of setup/hold warnings in my VHDL/Verilog simulations.

Many thanks!

  • 0
    TI__Mastermind 43660 points

    Hello John,

    Is there any device connected to CS0 ?

    To my opinion, the CS3 is intended for asynchronous operation only and you cannot do synchronous accesses using CS3.

    When using CS3, the EMA_CLOCK from EMIFA controller is asynchronous clock and it is no more syncing with other signals. The EMA_CLOCK signal in timing diagrams is to represent the signal behaviors with respect to clock cycle.

    Regards,

    Senthil

  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 100 points

    Hi Sentil,

    Thanks for the feedback. We already have a synchronous memory on CS0, and we have two more FPGA's on the bus (using CS3 and CS4).

    From the commonality of timing in the sync and async tables (1ns mins and 7ns max in sync, and nom +/-3ns for async being a 6ns spread), I assumed all the EMIF outputs (Data, Addr, OEF, WEF, RWF, and CSn for all n) were generated synchronously and clocked out of the 6748 device with the same timing regardless of which Chip Select was asserted;

    i.e.,  the 6748 was really always operating synchronously, but the external device (FPGA) could operate asynchronously if needed and timing specs were provided for designers who needed to use it that way.

    Sorry for my bad assumption, but thank you for the clarification.