This topic of EMIF address mapping has generated many threads, but I haven't seen one yet that clearly answers it for a 6748 device. Sorry if this is a rehash.
My group is designing a board with a 6748 EMIF interfaced to an FPGA. We are using EMIF CS3 to select the FPGA, and only implementing 2K FPGA registers inside the CS3 address space (0x6200 0000 to 0x63FF FFFF)
We're using the EMIF in 16-bit mode, and software will have its registers for that space declared as unsigned 16-bit types, so all reads and writes should be one atomic 16-bit transaction.
The EMIF address bus is connected to the FPGA as follows:
EMA_A[9] --> FPGA_ADDR[10]
EMA_A[8] --> FPGA_ADDR[9]
...
EMA_A[0] --> FPGA_ADDR[1]
EMA_BA[1] --> FPGA_ADDR[0]
EMA_BA[0] is not connected
This gives us, from the FPGA's perspective, 2^11 16-bit registers in the address range 0-2047 (0x000 - 0x7FF).
My questions pertain to exactly how we describe the address space for our software team in a HW/SW interface document, and what behavior I will see on EMA_BA[1].
Obviously BA[1] must toggle in order to access even/odd addresses inside the FPGA.
When software in the 6748 accesses the lowest FPGA register (FPGA address 0x000) I assume that corresponds to DSP/EMIF address 0x62000000, with (binary) EMA_A[9:0] = "0000000000" and BA[1] = 0.
For the 2nd register (FPGA address 0x001), the FPGA needs to see EMA_A[9:0] = "0000000000" and BA[1] = 1.
For the 3rd register (FPGA address 0x002), the FPGA needs to see EMA_A[9:0] = "0000000001" and BA[1] = 0.
For the 4th register (FPGA address 0x003), the FPGA needs to see EMA_A[9:0] = "0000000001" and BA[1] = 1.
etc...
How do I specify these addresses and addressing modes to the software guys in terms of absolute DSP addresses?
DSP(0x62000000) = FPGA(0x000) ?
DSP(0x62000001) = FPGA(0x001) ?
DSP(0x62000002) = FPGA(0x002) ?
DSP(0x62000003) = FPGA(0x003) ?
This seems counterintuitive, because it appears the Address LSB ( EMA_A[0] ) is advancing and BA[1] is not specified, so these accesses would skip every other FPGA register, unless those addresses are software-specific and the EMIF hardware translates them.
I could see
DSP(0x62000000) with (BA[1]=0) = FPGA(0x000) ?
DSP(0x62000000) with (BA[1]=1) = FPGA(0x001) ?
DSP(0x62000001) with (BA[1]=0) = FPGA(0x002) ?
DSP(0x62000001) with (BA[1]=1) = FPGA(0x003) ?
but then you have the problem of two different FPGA registers getting accessed by the same DSP address, and I don't know how the source code would be written to resolve that, unless it thought of DSP(0x62000000) as a 32-bit word, pulling in FPGA(0x000) as the lower half and FPGA(0x001) as the upper half, etc...
The other explanation I've heard is
DSP(0x62000000) = FPGA(0x000) ?
DSP(0x62000002) = FPGA(0x001) ?
DSP(0x62000004) = FPGA(0x002) ?
DSP(0x62000006) = FPGA(0x003) ?
In this case, the assumption is that everything is byte-addressable, and when accessing
DSP(0x62000000), you would get the lower byte of what's in FPGA(0x000) ?
DSP(0x62000001), you would get the upper byte of what's in FPGA(0x001) ?
DSP(0x62000002), you would get the lower byte of what's in FPGA(0x002) ?
DSP(0x62000003), you would get the upper byte of what's in FPGA(0x003) ?
etc...
but since it's a 16-bit access, you would only NEED to access the even addresses (0x62000000, 0x62000002, etc...)
This still requires the EMIF controller do the translations from internal addresses to external EMA_A[22:0] and BA[1:0] pins so the FPGA sees
EMA_A[9:0] = "0000000000" and BA[1] = 0.
EMA_A[9:0] = "0000000000" and BA[1] = 1.
EMA_A[9:0] = "0000000001" and BA[1] = 0.
EMA_A[9:0] = "0000000001" and BA[1] = 1.
Without a timing diagram, development board, or a simulation model (which I'm trying to write), I don't know whether to choose Door #1, Door #2, or Door #3...
Thanks for any insight you can provide!
