EDMA3_1 transfer not starts

Denis V.A.

Hello.

I need to transfer a data blocks between NAND (uses memory mapped fixed address) and DDR memory buffer. I`m using OMAP L138, DSP core. So I configure EDMA manual transfer between DDR buffer and a fixed address. It works well on the EDMA3_0, but unexpectedly transfer not starts on EDMA3_1. Initialization is the same in both cases.

It looks like transfer request was not passed to the TC for some reason (TC2 registers did not changed). In debugger I could see corresponding SER bit set after I set manual event. Documentation says it could happen if PaRAM is NULL-transfer when the event comes, but it is not my case. What else could prevent TC2 from handling this transfer? Is it enough to enable TC2 in PSC or some additional configuration required?

Thanks for your help.

over 9 years ago

0 Titusrathinaraj Stalin over 9 years ago

TI__Guru** 116100 points

Hi Denis,

Have you checked the EDMA3_1 initializations ?

Try to compare the both working and non-working EDMA3 init portion of code.

0 Denis V.A. over 9 years ago in reply to Titusrathinaraj Stalin

Prodigy 50 points

I using same initialization procedure for both EDMA3 that differs only in parameters like base addresses.

Here is startup initialization. It uses some of StarterWare functions.

  // Enabling the PSC for EDMA3 CCs.
  PSCModuleControl(SOC_PSC_0_REGS, HW_PSC_CC0, PSC_POWERDOMAIN_ALWAYS_ON, PSC_MDCTL_NEXT_ENABLE);
  PSCModuleControl(SOC_PSC_1_REGS, HW_PSC_CC1, PSC_POWERDOMAIN_ALWAYS_ON, PSC_MDCTL_NEXT_ENABLE);
  
  // Enabling the PSC for EDMA3 TCs.
  PSCModuleControl(SOC_PSC_0_REGS, HW_PSC_TC0, PSC_POWERDOMAIN_ALWAYS_ON, PSC_MDCTL_NEXT_ENABLE);
  PSCModuleControl(SOC_PSC_0_REGS, HW_PSC_TC1, PSC_POWERDOMAIN_ALWAYS_ON, PSC_MDCTL_NEXT_ENABLE);
  PSCModuleControl(SOC_PSC_1_REGS, HW_PSC_TC2, PSC_POWERDOMAIN_ALWAYS_ON, PSC_MDCTL_NEXT_ENABLE);
  
  // Initialization of EDMA3.
  EDMA3Init(SOC_EDMA30CC_0_REGS, 0);
  EDMA3Init(SOC_EDMA31CC_0_REGS, 0);

After that somewhere in code:

  memset (&g_NandEdmaPaRAM, 0, sizeof(EDMA3CCPaRAMEntry));

  g_NandEdmaPaRAM.srcAddr  = (u32)pSrc;
  g_NandEdmaPaRAM.destAddr = (u32)pDst;
  
  g_NandEdmaPaRAM.aCnt = (u16)1;
  g_NandEdmaPaRAM.bCnt = (u16)coData;
  g_NandEdmaPaRAM.cCnt = (u16)1;
  
  g_NandEdmaPaRAM.srcBIdx  = (u16)(nIncr >> 16);
  g_NandEdmaPaRAM.destBIdx = (u16)(nIncr & 0xFFFF);
  
  g_NandEdmaPaRAM.linkAddr = (u16)0xFFFF;
  
  g_NandEdmaPaRAM.opt = 0u;
  g_NandEdmaPaRAM.opt |= ((NAND_EDMA_CHAN << EDMA3CC_OPT_TCC_SHIFT) & EDMA3CC_OPT_TCC); // Set TCC number.
  g_NandEdmaPaRAM.opt |= EDMA3CC_OPT_TCINTEN | EDMA3CC_OPT_SYNCDIM;
  
  HWREG(NAND_EDMA_TC + EDMA3TC_RDRATE) = EDMA3TC_RDRATE_RDRATE_32CYCLE;
  
  // Start exchange.
  EDMA3SetPaRAM       (NAND_EDMA_CC, NAND_EDMA_CHAN, &g_NandEdmaPaRAM);
  EDMA3EnableTransfer (NAND_EDMA_CC, NAND_EDMA_CHAN, EDMA3_TRIG_MODE_MANUAL);

This code uses #defines that I could change:

  #define NAND_EDMA_CCNUM     0
  #define NAND_EDMA_CC        SOC_EDMA30CC_0_REGS
  #define NAND_EDMA_TC        SOC_EDMA30TC_0_REGS
  //#define NAND_EDMA_CHAN      28
  #define NAND_EDMA_CHAN    EDMA3_PRU_EVTOUT6

I works on EDMA3_0 both on TC0 and TC1, but transfer did not start on EDMA3_1. I could see in debugger, that despite of successful setting ESR bit only corespoding SER bit are set. Nothing changes in queue registers (CC queue stays empty), nothing changes in TC2 (stays idle).

I have checked manually through debugger that PSC is configured and CC and TC2 should be enabled. So I really wonder what could prevent it from work.

Whole problem is that there is a time-critical SPI transfer running on EDMA3_0 TC0 by the ARM core and occasional UART data receive (~50 bytes) by the DSP core. And when I trying to run NAND data block read or write (4 Kb of data) it causes real-time SPI to work wrong, and UART exchange hangs at all. So I trying to split 4K into few smaller transfers (64 bytes) running on other EDMA3 instance with lower priority. Running it on TC1 does not helps, so I decided to try on EDMA3_1.

0 Mukul Bhatnagar over 9 years ago in reply to Denis V.A.

TI__Guru* 78325 points

Dennis

I think you are triggering an event to a null set some how. This would typically be if you thought you are triggering a channel and have a corresponding param set associated to it, but the paramset does not have the transfer context initialized.

Can you double check your event - channel - param mapping?

I see that you are trying to use

EDMA3_PRU_EVTOUT6 (which is event/channel 20  in EDMA3 CC0) ...assuming this works for CC1 too, I think from your code , you were using channel/event 28 when you were using CC0?
Can you make sure ParamSet 20 is programmed correctly or use event/channel 28 instead?

Regards
Mukul

0 Denis V.A. over 9 years ago in reply to Mukul Bhatnagar

Prodigy 50 points

Triggering null set was the first I had checked, because it is mentioned in the documentation as a possible reason for such situations. Unfortunately it is not the reason. I have checked several times through the debugger that I prepare exactly same PaRAM set as the event bit number I trigger.

I always use EDMA3_PRU_EVTOUT6 (ch# 20) for the EDMA3 CC0, and I have tested same ch#20 for the CC1, and also tried ch#28 for CC1.

0 Mukul Bhatnagar over 9 years ago in reply to Denis V.A.

TI__Guru* 78325 points

Ok, if you have SER set transfer will not happen. Need to figure out why SER is set.

Can you send a memory dump of your CC1 , TC2 and ParamSet registers for the failing condition?

0 Denis V.A. over 9 years ago in reply to Mukul Bhatnagar

Prodigy 50 points

Ok, I will send dumps, but little later. Right now the device becomes unavailable for me for some time. I will write here again.

0 Denis V.A. over 9 years ago in reply to Denis V.A.

Prodigy 50 points

Sorry for a long delay. I have just got the device back.

While taking dump I found a strange thing: when I start transfer, ERRSTAT`s MMR bit (address error event) was set. But both addresses seems valid: one is 0x62000000 (NAND data register) and one is my buffer.

Dumps are attached. Summary:

PaRAM #28:
----------

OPT		0x8111`C004 - PRIVID=1, TCINTEN=1, TCC=28, FWID=8, SYNCDIM=ABSYNC.
SRC		0x6200`0000 - NAND_FLASH_BASE_ADDR.
A_B_CNT		0x0040`0001 - Bcnt = 64, Acnt = 1.
DST		0xC201`0400 - Some DDR buffer aligned on 64-byte boundary.
SRC_DST_BIDX	0x0001`0000 - Dst - +1, Src - fixed.
LINK_BCNTRLD	0x0000`FFFF - Bcnd reload = 0, Link = 0xFFFF (null).
SRC_DST_CIDX	0x0000`0000 - C indexes are zero, do not use 3D.
CCNT		0x0000`0001 - Ccnt = 1.

CC registers BEFORE xfer start:
-------------------------------

IER		0x1000`0000 - Bit 28 is set.
IPR		0x0000`0000 - No pending interrupts.

ER		0x0000`0000 - No events.
ER global	0x0004`0000 - Event #18 are set (GPIO), event #28 are clear.
ESR		0x0000`0000 - No events in event set register.
EER		0x0000`0000 - All hw events disabled.
SER		0x0000`0000 - No events here as well.

DRAE1		0x1000`0000 - Region 1 (DSP) owns event #28. Other DRAEs and QRAEs are zeros.

Q0E0..Q0E15	Filled with some random data.

DMAQNUM3	0x0001`0000 - E4=1.

REV		0x4001`9B00
CCFG		0x0020`3344

Other registers are zeros.

TC2 registers BEFORE xfer start:
--------------------------------

TPTCSTAT	0x0000`0100 - all empty/idle.
RDRATE		0x0000`0004 - Set by me, 32-cycle delay. Nothing changes if leave default.

REV		0x4000`8B00
TCCFG		0x0000`0213


Register changes AFTER xfer start:
----------------------------------

ESR		0x1000`0000 - Event #28 set by me.
SER		0x1000`0000 - Event #28.
CCSTAT		0x0000`0011 - ACTV bit becomes 1=BUSY, EVTACTV bit becomes 1=ACTIVE.

TC regisetrs:

ERRSTAT		0x0000`0008 - MMR address error event.

No other changes in CC or TC.

dumps.zip

0 Mukul Bhatnagar over 9 years ago in reply to Denis V.A.

TI__Guru* 78325 points

Hi
I would've preferred if you would've used the CCS register view/save option to save the CC/TC register content.

However with just the snapshot you in the post (ignoring the memory dump)

Denis V.A. said:
DMAQNUM3 0x0001`0000 - E4=1

There is a note in the EDMA documentation for DMAQNUM registsers, Available only for EDMA3_0_CC0; for EDMA3_1_CC0, this value is reserved and all events are queued on Q0

Assuming you are using EDM3_1_CC0, and you want to use TC2, you will need to program this DMAQNMUM register to its default Q0 only as there is no Q1

See figure 18-1 in the beginning of EDMA chapter.

Essentially what you call TC2 (3rd transfer controller in the device) is TC0 for the second CC (EDMA3_1_CC0) in the system.

Additionally do not worry about ERRSTAT. This is not documented in EDMA user guide, but emulation access to TC register space will cause the MMR address error to set. In normal course (non debug mode) this will not happen and you should be able to ignore this error.

Hoping this helps.

If not, please send your register memory dump, via CCS register view save method.

Regards

Mukul

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EDMA3_1 transfer not starts