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uPP DMA EOLI to late

Other Parts Discussed in Thread: OMAP-L138, ADS8558

I use the OMAP-L138 and an ADS8558.
They are linked through the uPP.
On GPIO bank 6 I generate the CONVST, CS, RD (ADS) and ENABLE, CLOCK (uPP) signals.
The uPP-STARTA Signal is disabled (UPICR).
CS, RD and CLOCK are driven by one GPIO together.


The dma-descriptor is configured to get 6 words:

    if (!CSL_FEXT(upp0Regs->UPIS2, UPP_UPIS2_PEND)
            && !CSL_FEXT(upp0Regs->UPIS2, UPP_UPIS2_ACT))
        upp0Regs->UPID0 = (uint32_t) &uppInputBuffer;
        upp0Regs->UPID1 = CSL_FMK(UPP_UPID1_LNCNT, 1)
                | CSL_FMK(UPP_UPID1_BCNTH, 6);
        upp0Regs->UPID2 = (0);
    }


But the following loop exits after 11 cycles:

    // CLK/RD until EOLI/EOWI/ERROR:
    while (upp0Regs->UPIER == 0) {
        // CLK/CS/RD low:
        *gpio_bank6_out_data = gpio_b6_state[state_ADS_CONVST_H_ADS_CS_L_UPP_EN_L];
        // CLK/CS/RD high:
        *gpio_bank6_out_data = gpio_b6_state[state_ADS_CONVST_H_ADS_CS_H_UPP_EN_L];
    }

In uppInputBuffer[0]..[5] are the datas, uppInputBuffer[6] is untouched, but the datas are at wrong order:
I have to reorder it whith this statement:

    inputData[0] = uppInputBuffer[4]);
    inputData[1] = uppInputBuffer[5]);
    inputData[2] = uppInputBuffer[0]);
    inputData[3] = uppInputBuffer[1]);
    inputData[4] = uppInputBuffer[2]);
    inputData[5] = uppInputBuffer[3]);

My questions:
1.) Why it takes 11 clocks?
2.) Why it is in wrong order?

Can help somebody?

Andreas


--
PS. uPP conf:

    // uPP Channel Control Register
    upp0Regs->UPCTL = CSL_FMKT(UPP_UPCTL_MODE, RECEIVE)
            | CSL_FMKT(UPP_UPCTL_CHN, ONE)
            | CSL_FMKT(UPP_UPCTL_SDRTXIL, DISABLE)
            | CSL_FMKT(UPP_UPCTL_DDRDEMUX, DISABLE)
            | CSL_FMKT(UPP_UPCTL_DRA, SINGLE) | CSL_FMKT(UPP_UPCTL_IWA, 16BIT)
            | CSL_FMKT(UPP_UPCTL_DPWA,FULL);

    // uPP Interface Configuration Register
    upp0Regs->UPICR = CSL_FMKT(UPP_UPICR_STARTA, DISABLE)
    | CSL_FMKT(UPP_UPICR_ENAPOLA, INVERT) | CSL_FMKT(UPP_UPICR_ENAA, ENABLE)
            | CSL_FMKT(UPP_UPICR_CLKINVA, NORMAL)
            | CSL_FMKT(UPP_UPICR_STARTPOLA, INVERT);

    // idle value register
    upp0Regs->UPIVR = CSL_FMKT(UPP_UPIVR_VALA, RESETVAL);

    // uPP Threshold Configuration Register
    upp0Regs->UPTCR = CSL_FMKT(UPP_UPTCR_RDSIZEI, 64B);

    // uPP Interrupt Enable Set Register
    upp0Regs->UPIES = CSL_FMKT(UPP_UPIES_EOLI, SET)
            | CSL_FMKT(UPP_UPIES_EOWI, SET);

    // DLB:
    CSL_FINST(upp0Regs->UPDLB, UPP_UPDLB_BA, DISABLE);
    CSL_FINST(upp0Regs->UPDLB, UPP_UPDLB_AB, DISABLE);

    // uPP Peripheral Control Register
    CSL_FINST(upp0Regs->UPPCR, UPP_UPPCR_EN, ENABLE);




  • Hi Andreas,

    How did you configure the uPP peripheral ?

    Please provide us the brief configuration about your uPP peripheral.

    uPP freq, mode etc.,

    Have you configured 'EOW' interrupt generation instead configuring to 'EOL'

  • Ok, I wanna decribe it a little bit more.

    I use the OMAP-L138 (ZOOM Logic PD, development kit) with a breakout board on J29 and connected it with a ADS8558EVM (TI). I want to sample 6 channels (each has 12 bit, on the uPP-Input the higher 4 bits (12..15) are connected to bit 11 (sign-bit))

    This 16 wires from ADS are connected to uPP CH-A (UPP_CH1D[0..15]).

    uPP Channel Control Register (UPCTL):

    • Receive Mode, ONE: CHANNEL A
    • Single Channel Mode
    • Single Data Rate
    • 16-bit Interface FULL

    uPP Interface Configuration Register (UPICR):

    • StartA is disabled
    • EnableA is active low
    • EnableA is enabled
    • CLKINVA is normal (not inverted)
    • STARTPOLA is inverted

    uPP Threshold Configuration Register (APTCR)

    • threshold 64B

    uPP Interrupt Enable Set Register (UPIES):

    • EOLI and EOWI are set (enabled)

    uPP Digital Loopback Register (UPDLB):

    • disabled

    DMA descriptor:

    • 1x line with 6 values (16 bit)
    • UPID0 = (uint32_t) &uppInputBuffer;
    • UPID1->LNCNT = 1 (one line)
    • UPID1->BCNTH = 6 (6 data, 16 bit)
    • UPID2 = 0 (line offset)

    uPP signals:

    • UPP_CH1_ENABLE and UPP_CH1_CLK are generated in the programm and set GPIO (GP6[0], PIN68 and GP6[2], PIN31). This GPIOs are connected to PIN69 (UPP_CH1_ENABLE) and PIN67 (UPP_CH1_CLK)

    uPP DMA:

    • Because of there is only 1 line, EOLI and EOWI switch at the same time to high. This works fine, but to late.

    After CONVST-signal set high and BUSY becomes low the CLK-signal is self generated in a loop using GPIO (PIN31).
    This CLK-signal is connected to the ADS8558 RD and CS and the UPP-CH1-CLK (PIN67) too.

    On falling edge of CLK/RD the next data is requested (ADS8558), on rising edge the uPP DMA will import it.

    The while loop exits if UPIER is not null (for example EOLI):

        // CLK/RD until EOLI/EOWI/ERROR:
        while (upp0Regs->UPIER == 0) {
            // CLK/CS/RD low:
            *gpio_bank6_out_data = gpio_b6_state[state_ADS_CONVST_H_ADS_CS_L_UPP_EN_L];
            // CLK/CS/RD high:
            *gpio_bank6_out_data = gpio_b6_state[state_ADS_CONVST_H_ADS_CS_H_UPP_EN_L];
        }

        // EOLI/EOWI (only for debug)
        CSL_FINS(gpioRegs->BANK[GP6].OUT_DATA, GPIO_OUT_DATA_OUT13, 1);
        CSL_FINS(gpioRegs->BANK[GP6].OUT_DATA, GPIO_OUT_DATA_OUT13, 0);

         // End of Interrupt Vector -> after uPP interrupt to allow interrupt generation from subsequent uPP events
         CSL_FINS(upp0Regs->UPEOI, UPP_UPEOI_EOI, 0);

         // set CONVST_A low:
        *gpio_bank6_out_data = gpio_b6_state[state_ADS_CONVST_L_ADS_CS_H_UPP_EN_H];

       

    And now I do not understand why there are 11 CLK-cycles (I expected 6 CLK-cycles).

     

    At the scrrenshot you can see:

    1. the CONVST-signal: ADS8558 start conversion
    2. BUSY: ADS8558 is not ready
    3. CLK/RD: the self generated clock until EOLI
    4. if EOLI/EOWI is detected I set a GPIO high and low of reasons for debug
    5. ENABLE: enable/disable the uPP DMA

  • Hello!

    I'm getting the same effect.

    I tried to figure this out since weeks and have no clue how to avoid these disaligned data.

    Would you please provide help to this topic?!

    Regards

    Torsten