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C6748/OMAP-L138: uPP Cache Coherence?

Bernd Sprenger
Prodigy 110 points

Hello,

we attached a FPGA to a L138 by using the uPP. The C674x core is set up to use L2 as internal memory and L1 as cache. The DMA of the UPP transmittes/receives data directly to the L2 memory. In "SPRUG82A - TMS320C674x DSP Cache User's Guide", in section 2.4.1/2.4.2 (page 27-29) the "Snoop Coherence Protocol" between L1D and L2-SRAM for DMA accesses is described. Only EDMA/IDMA are mentioned on page 26 to support the "Snoop Coherence Protocol". Since the UPP-peripheral has its own DMA in it, I am not sure if this uPP-DMA is also supported by this hardware cache coherence protocol. Otherwise we have to use the L1 cache invalidate/writeback schema...

Question: Is the uPP-DMA access to L2-SRAM supported by the mentioned "Snoop Coherence Protocol" between L2-SRAM-L1D?

Thanks a lot for your answer in advance,

Bernd Sprenger